POWER MEASUREMENT TECHNIQUES OF A SYSTEM-ON-CHIP (SOC)
First Claim
1. A method comprising:
- setting one or more interfaces of a system-on-chip (SOC) into an idle mode;
setting one or more processor cores in the SOC into an idle state;
disabling one or more clock inputs to the SOC;
reducing a voltage level of one or more logic blocks of the SOC, the one or more logic blocks having a common voltage plane; and
measuring a power consumption of the SOC.
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Abstract
A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.
57 Citations
26 Claims
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1. A method comprising:
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setting one or more interfaces of a system-on-chip (SOC) into an idle mode; setting one or more processor cores in the SOC into an idle state; disabling one or more clock inputs to the SOC; reducing a voltage level of one or more logic blocks of the SOC, the one or more logic blocks having a common voltage plane; and measuring a power consumption of the SOC. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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setting one or more interfaces of a system-on-chip (SOC) into an active mode; setting one or more processor cores in the SOC into an idle state; enabling one or more clock inputs to the SOC; providing communication traffic to the SOC; and measuring a power consumption of the SOC. - View Dependent Claims (9, 10, 11, 12, 13)
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14. An apparatus comprising:
power management logic to; control one or more power gates, each power gate coupled with a voltage input and a power domain of one or more logic blocks; and control one or more clock inputs to the one or more logic blocks. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. The apparatus of 14, further comprising a module coupled with the processor and the power management logic to simulate a read command and a write command of the processor when the processor is set in an idle mode.
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25. The apparatus of 24, further comprising a switch module coupled with the module and the one or more interfaces to:
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determine that communication traffic from the one or more interfaces does not require processing by the processor; and route the communication traffic among the one or more interfaces without any processing by the processor.
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26. The apparatus of 25, wherein the switch module to determine that the communication traffic from the one or more interfaces does not require processing by the processor is to check that a header of the communication traffic indicates that the communication traffic is not directed to the processor.
Specification