METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH MEMORY

• US 20110060969A1
• Filed: 11/15/2010
• Published: 03/10/2011
• Est. Priority Date: 01/20/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Ramamoorthy, Aditya, Sutardja, Pantas, Wu, Zining
• Granted Patent: US 8,473,812 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 2212/403 Error protection encoding, e.g. using parity or ECC codes
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2207/16 Solid state audio
• CPC Class Codes: G11C 2211/562 Multilevel memory programming aspects
• CPC Class Codes: G11C 2211/563 Multilevel memory reading aspects
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: H03M 13/1177 Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes

Abstract

A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.

Claims

1. A controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the controller configured to:

encode a series of data bits to generate a series of encoded data bits;

convert the series of encoded data bits into a series of data symbols;

send, to the memory array, a stored series of data symbols based on the series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array;

generate an output signal based on data associated with the stored series of data symbols, the output signal characterized by a second number of digital levels greater than the first number of digital levels used to store the series of data symbols in the memory cell; and

output a series of output data symbols based on the output signal.

2. The controller of claim 1 comprising:

a first encoder;

a first decoder;

a second encoder in communication with the first encoder; and

a second decoder in communication with the first decoder.

3. The controller of claim 2 wherein the first encoder is adapted to perform a first ECC technique and the second encoder is adapted to perform a second ECC technique.

4. The controller of claim 3 wherein the first ECC technique is different from the second ECC technique.

5. The controller of claim 1 wherein the multi-level solid state non-volatile memory array comprises one or more flash EEPROM arrays.

6. The controller of claim 1 wherein the output signal is generated based on soft information.

7. A method of operating a controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the method comprising:

encoding a series of data bits to generate a series of encoded data bits;

converting the series of encoded data bits into a series of data symbols;

sending, to the memory array, a stored series of data symbols based on the series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array;

generating an output signal based on data associated with the stored series of data symbols, the output signal characterized by a second number of digital levels greater than the first number of digital levels used to store the series of data symbols in the memory cell; and

outputting a series of output data symbols based on the output signal.

8. The method of claim 7 further comprising:

encoding data bits to generate the series of data bits; and

decoding the series of output data symbols.

9. The method of claim 8 wherein the encoding of the data bits is performed in accordance with a first ECC technique and the encoding of the series of data bits is performed in accordance with a second ECC technique.

10. The method of claim 9 wherein the first ECC technique is different from the second ECC technique.

11. The method of claim 7 wherein the multi-level solid state non-volatile memory array comprises one or more flash EEPROM arrays.

12. The method of claim 7 wherein the output signal comprises soft information.

13. A controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the controller comprising:

means for encoding a series of data bits to generate a series of encoded data bits;

means for converting the series of encoded data bits into a series of data symbols;

means for sending, to the memory array, a stored series of data symbols based on the series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array;

means for generating an output signal based on data associated with the stored series of data symbols, the output signal characterized by a second number of digital levels greater than the first number of digital levels used to store the series of data symbols in the memory cell; and

means for outputting a series of output data symbols based on the output signal.

14. The controller of claim 13 further comprising:

means for encoding data bits to generate the series of data bits; and

means for decoding the series of output data symbols.

15. The controller of claim 14 wherein the encoding of the data bits is performed in accordance with a first ECC technique and the encoding of the series of data bits is performed in accordance with a second ECC technique.

16. The controller of claim 15 wherein the first ECC technique is different from the second ECC technique.

17. The controller of claim 13 wherein the multi-level solid state non-volatile memory array comprises one or more flash EEPROM arrays.

18. The controller of claim 13 wherein the output signal comprises soft information.