Device and methods for optimizing communications between a medical device and a remote electronic device

• US 20110063094A1
• Filed: 12/23/2009
• Published: 03/17/2011
• Est. Priority Date: 06/29/2007
• Status: Active Grant

• Current Assignee: Roche Diabetes Care Inc. (Roche Holding AG)
• Original Assignee: Roche Diagnostics Operations Incorporated (Roche Holding AG)
• Inventors: Oberil, Markus, Sabol, Peter, von Bueren, Thomas, Frikart, Marcel, Anliker, Urs, Jungen, Markus, Buck, Harvey JR., Strickland, Raymond, Meiertoberens, Ulf, Fehr, Jean-Neol, Celentano, Michael J.
• Granted Patent: US 8,680,974 B2
• Time in Patent Office: Days
• US Class Current: 340/12.5
• CPC Class Codes: A61B 5/0002 Remote monitoring of patients using telemetry, e.g. transmission of vital signals via a communication network A61B5/07 takes precedence; transmission systems for measured values G08C; transmission H04B; transmission of digital information H04L; wireless communication networks H04W
• CPC Class Codes: A61B 5/14532 for measuring glucose, e.g. by tissue impedance measurement
• CPC Class Codes: A61M 2205/3569 sublocal, e.g. between console and disposable
• CPC Class Codes: A61M 2205/3592 using telemetric means, e.g. radio or optical transmission
• CPC Class Codes: A61M 2205/502 User interfaces, e.g. screens or keyboards
• CPC Class Codes: A61M 2209/01 Remote controllers for specific apparatus
• CPC Class Codes: A61M 5/14244 adapted to be carried by the patient, e.g. portable on the body
• CPC Class Codes: A61M 5/172 electrical or electronic A61M5/16804, A61M5/16831 take precedence
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

An electronic device may communicate wirelessly with another electronic device. The electronic device may include a first processor configured to control only wireless communications with the another device but not operations associated only with the electronic device, a second processor configured to control the operations associated only with the electronic device but not the wireless communications with the another device, and a memory device connected between the first and second processors. The first and second processors may each be configured to exchange information with the memory device separately and independently of the exchange of information by the other of the first and second processors with the memory device.

Claims

1. An electronic device for communicating wirelessly with another electronic device, the electronic device comprising:

a first processor configured to control only wireless communications with the another device but not operations associated only with the electronic device,

a second processor configured to control the operations associated only with the electronic device but not the wireless communications with the another device, and

a memory device connected between the first and second processors, the first and second processors each configured to exchange information with the memory device separately and independently of the exchange of information by the other of the first and second processors with the memory device.

2. The electronic device of claim 1 further comprising a first one of a synchronous and an asynchronous interface electrically connected between the first processor and the memory device,

and wherein the first processor is configured to send information wirelessly received from the another electronic device to the memory device via the first one of the synchronous and asynchronous interface, and to retrieve information to be communicated wirelessly to the another electronic device from the memory device via the first one of the synchronous and asynchronous interface.

3. The electronic device of claim 2 further comprising a second one of a synchronous and an asynchronous interface electrically connected between the second processor and the memory device

and wherein the second processor is configured to retrieve from the memory device via the second one of the synchronous and asynchronous interface the information wirelessly received from the another electric device and sent to the memory device by the first processor, and to send to the memory device via the second one of the synchronous and asynchronous interface the information to be communicated wirelessly to the another electronic device by the first processor.

4. The electronic device of claim 3 wherein the memory device comprises an outbound buffer that is configured to store therein the information sent to the memory device by the second processor and that is to be communicated wirelessly to the another electronic device by the first processor, the outbound buffer being in data communication with the first and second ones of the synchronous and asynchronous interfaces.

5. The electronic device of claim 4 wherein the memory device comprises an inbound buffer that is configured to store therein the information wirelessly received from the another electric device and sent to the memory device by the first processor and that is to be retrieved from the memory device by the second processor, the inbound buffer being in data communication with the first and second ones of the synchronous and asynchronous interfaces.

6. The electronic device of claim 5 wherein the first processor is configured to incorporate the information retrieved from the outbound buffer into a wireless communications protocol structure, and to then wirelessly transmit the incorporated information to the another electronic device using the wireless communication protocol.

7. The electronic device of claim 6 wherein the wireless communication protocol is a radio frequency communication protocol.

8. The electronic device of claim 5 wherein the first processor is configured to wirelessly receive information incorporated into a wireless communication protocol structure from the another electronic device, to isolate the information from the wireless communication protocol structure and to then send the isolated information to the inbound buffer of the memory device.

9. The electronic device of claim 8 wherein the wireless communication protocol is a radio frequency communication protocol.

10. The electronic device of claim 5 wherein the second processor is configured to send the information to the memory device by requesting, asynchronously with respect to operation of the first processor, the state of the outbound buffer of the memory device and to send the information to the memory device only if the memory device indicates that the outbound buffer is not full, and to otherwise wait for a time period before again requesting, asynchronously with respect to operation of the first processor, the state of the outbound data buffer of the memory device.

11. The electronic device of claim 5 wherein the second processor is configured to retrieve from the memory device the information wirelessly received from the another electric device and sent to the memory device by the first processor by periodically, and asynchronously with respect to operation of the first processor, requesting the state of the inbound buffer of the memory device, the second processor configured to retrieve the information from the inbound buffer of the memory device only if the memory device indicates that the inbound buffer contains information, and to otherwise continue to periodically, and asynchronously with respect to operation of the second processor, request the state of the inbound data buffer.

12. The electronic device of claim 5 wherein the first one of the synchronous and asynchronous interface is an asynchronous interface that includes a clear to send (CTS) signal line,

and wherein the first processor is configured to activate the CTS signal line whenever the first processor is requesting data and to otherwise deactivate the CTS signal line.

13. The electronic device of claim 12 wherein the first processor is configured to request the information to be communicated to the another electronic device from the memory device by periodically, and asynchronously with respect to operation of the second processor and operation of the memory device, activating the CTS signal line and retrieving the information to be wirelessly communicated to the another electronic device from the outbound buffer only if the outbound buffer contains data, and to otherwise continue to periodically, and asynchronously with respect to operation of the second processor and operation of the memory device, activate the CTS signal line.

14. The electronic device of claim 5 wherein the first one of the synchronous and asynchronous interface is an asynchronous interface that includes a ready to send (RTS) signal line,

and wherein the memory device is configured to activate the RTS signal line whenever the inbound data buffer is not full and to otherwise deactivate the RTS signal line.

15. The electronic device of claim 13 wherein the first processor is configured to send the information wirelessly received from the another electronic device to the memory device by periodically, and asynchronously with respect to operation of the second processor and operation of the memory device, monitoring the RTS signal line and sending the information wirelessly received from the another electronic device to the inbound buffer of the memory device only if the RTS signal line is activated, and to otherwise continue to periodically, and asynchronously with respect to operation of the second processor and operation of the memory device, monitor the RTS signal line.

16. The electronic device of claim 1 further comprising:

one or more batteries,

a first power supply configured to produce a first supply voltage derived from the one or more batteries and provide the first supply voltage to the first second processor and to the memory unit, and

a second power supply configured to produce a second supply voltage derived from the one or more batteries and to provide the second supply voltage to the first processor,

wherein the memory device comprises a third processor.

17. The electronic device of claim 16 further comprising an on/off switch,

wherein the memory device is configured to be responsive to an on signal produced by the on/off switch to enable the second power supply to produce the second supply voltage, and to an off signal produced by the on/off switch to command orderly shutdown of the first processor and to then disable the second power supply such that the second power supply no longer produces the second supply voltage.

18. The electronic device of claim 16 further comprising:

a test element receiving port configured to receive a test element,

electronic circuitry configured to detect insertion of the test element into the test element receiving port and to produce a corresponding strip insert signal,

a fourth processor configured to analyze a liquid sample provided on the test element to determine a concentration of an analyte in the liquid sample, the fourth processor configured to be responsive to the strip insert signal to provide a strip insertion message to the memory device,

wherein the memory device configured to be responsive to the strip insertion message to command orderly shutdown of the first processor and to then disable the second power supply such that the second power supply no longer produces the second supply voltage.

19. The electronic device of claim 18 wherein the fourth processor is configured to provide a test complete message to the memory device when the concentration of the analyte is determined by the fourth processor,

and wherein the memory device is configured to be responsive to the test complete message to enable the second power supply such that the second power supply produces the second supply voltage.

20. The electronic device of claim 16 further comprising a plurality of user activated buttons or keys,

wherein if the first power supply is producing the first supply voltage and the second power supply is producing the second supply voltage, the memory device is responsive to one of a simultaneous activation of a predefined combination of two or more of the plurality of user activated buttons or keys, activation of a predefined sequence of two or more of the plurality of user activated buttons or keys and a dedicated one of the plurality of user activated buttons or keys to command orderly shutdown of the first processor and to then disable the second power supply such that the second power supply no longer produces the second supply voltage.

21. The electronic device of claim 16 further comprising a plurality of user activated buttons or keys,

wherein if the first power supply is producing the first supply voltage and the second power supply is disabled so that it is not producing the second supply voltage, the memory device is responsive to simultaneous activation of a predefined combination of two or more of the plurality of user activated buttons or keys to enable the second supply voltage so that it produces the second supply voltage.

22. The electronic device of claim 16 further comprising an on/off switch,

wherein the first power supply is enabled by an on signal produced by the on/off switch to produce the first supply voltage, and is disabled by an off signal produced by the on/off switch such that the first power supply does not produce the first supply voltage.

23. The electronic device of claim 22 further comprising a display unit,

wherein the second processor is configured, when the first power supply is enabled, to control the display unit to display an indication that a wireless connection between the electronic device and the another electronic device is not established.

24. The electronic device of claim 16 further comprising a voltage sense line electrically connected between the second power supply and the second processor, the voltage sense line carrying a sense voltage that is indicative of the supply voltage produced by the second power supply,

wherein the second processor is configured to be responsive to the sense voltage to store, asynchronously with respect to operation of the first processor, an acknowledgement response command in the memory device when the sense voltage indicates that the second power supply has been enabled to produce the second supply voltage after having been disabled such that the second power supply did not produce the second supply voltage.

25. The electronic device of claim 24 wherein the first processor is configured to retrieve, asynchronously with respect to operation of the second processor, the acknowledgment response command from the memory device, and to wirelessly transmit the acknowledgement transmit command.

26. The electronic device of claim 25 wherein the first processor is configured, if the another electronic device wirelessly transmits an acknowledgement response in response to receipt of the acknowledgement response command and the transmitted acknowledgement response is received by the first processor, to isolate the acknowledgement response from a wireless communication protocol structure used by the another electronic device to wirelessly transmit the acknowledgment response, and to then store the acknowledgement response in the memory unit asynchronously with respect to operation of the memory unit and operation of the second processor.

27. The electronic device of claim 26 further comprising a display unit,

wherein the second processor is configured to, asynchronously with respect to operation of the first processor, retrieve the acknowledgement response from the memory unit and to then control the display unit to display an indication that a wireless connection exists between the electronic device and the another electronic device.

28. The electronic device of claim 27 wherein the second processor is configured to periodically store the acknowledgement response command in the memory device asynchronously with respect to operation of the first processor, to then periodically check the memory device, asynchronously with respect to operation of the first processor, and to continue to control the display unit to display the indication that the wireless connection exists between the electronic device and the another electronic device as long as the second processor retrieves the acknowledgement response from the memory unit within a predefined time period following storage of the acknowledgement response command in the memory device.

29. The electronic device of claim 28 wherein the second processor is configured to control the display unit to display the indication that the wireless connection does not exist between the electronic device and the another electronic device if second processor does not retrieves the acknowledgement response from the memory unit within the predefined time period following storage of the acknowledgement response command in the memory device.

30. The electronic device of claim 16 further comprising:

a display unit, and

a voltage sense line electrically connected between the second power supply and the second processor, the voltage sense line carrying a sense voltage that is indicative of the supply voltage produced by the second power supply,

wherein the second processor is configured to be responsive to the sense voltage to control the display unit to display an indication that the second processor is producing the second supply voltage if the sense voltage indicates that the second processor is producing the second supply voltage.

31. The electronic device of claim 16 further comprising:

a display unit, and

a voltage sense line electrically connected between the second power supply and the second processor, the voltage sense line carrying a sense voltage that is indicative of the supply voltage produced by the second power supply,

wherein the second processor is configured to be responsive to the sense voltage to control the display unit to display an indication that the second processor is not producing the second supply voltage if the sense voltage indicates that the second processor is not producing the second supply voltage.

32. The electronic device of claim 16 further comprising:

an on/off switch,

a display unit,

a fourth processor configured to analyze a liquid sample provided on a test element to determine a concentration of an analyte in the liquid sample, the fourth processor configured to provide a test complete message to the second processor when the concentration of the analyte is determined by the fourth processor,

wherein the second power supply is disabled such that it does not produce the second supply voltage when the fourth processor is determining the concentration of the analyte in the liquid sample, the second power supply configured to be responsive to an on signal produced by the on/off switch to become enabled and produce the second supply voltage,

and wherein the second processor is configured to the responsive to the test complete message produced by the fourth processor to control the display unit to display a message that instructs the user to active the on/off switch to produce the on signal in order to communication wirelessly with the another electronic device.

33. The electronic device of claim 16 wherein the memory device comprises an outbound buffer that is configured to store therein information sent to the memory device by the second processor that is to be communicated wirelessly to the another electronic device by the first processor, the outbound buffer being in data communication with the first and second processors,

and wherein the memory device is configured to monitor a status of the outbound buffer and to control operation of the second power supply based on the status of the outbound buffer.

34. The electronic device of claim 33 wherein the memory device comprises a timer circuit,

and wherein the memory device is configured to reset the timer circuit each time the second processor stores information in the outbound buffer of the memory device,

and wherein the memory device is configured to maintain the second power supply enabled such that the second power supply produces the second supply voltage as long as the memory device resets the timer circuit when a predefined time period elapses since last resetting the timer circuit.

35. The electronic device of claim 34 wherein the memory device is configured to disable the second power supply such that the second power supply does not produce the second supply voltage if the memory device does not reset the timer circuit before the predefined time period elapses since last resetting the timer circuit.

36. The electronic device of claim 35 wherein the memory device is configured to reset the timer circuit when second processor stores information in the outbound buffer of the memory device while the second power supply is disabled,

and wherein the memory device is configured to enable the second power supply such that the second power supply produces the second supply voltage when the timer circuit is reset while the second power supply is disabled.

37. The electronic device of claim 35 further comprising:

a test element receiving port configured to receive a test element,

electronic circuitry configured to detect insertion of the test element into the test element receiving port and to produce a corresponding strip insert signal,

a fourth processor configured to analyze a liquid sample provided on the test element to determine a concentration of an analyte in the liquid sample, the fourth processor configured to be responsive to the strip insert signal to provide a strip insertion message to the second processor,

wherein the second processor is configured to cease storing information in the outbound buffer of the memory device when the fourth processor produces the strip insert message so that the memory device does not reset the timer circuit before the predefined time period elapses since last resetting the timer circuit and the memory device then disables the second power supply such that the second power supply does not produce the second supply voltage.

38. The electronic device of claim 37 wherein the fourth processor is configured to provide a test complete message to the second processor when the concentration of the analyte is determined by the fourth processor,

and wherein the second processor is configured to resume storing information in the outbound buffer of the memory device when the fourth processor produces the test complete message so that the memory device resets the timer circuit and the memory device then enables the second power supply such that the second power supply produces the second supply voltage.

39. The electronic device of claim 35 further comprising:

a test element receiving port configured to receive a test element,

a fourth processor configured to analyze a liquid sample provided on the test element to determine a concentration of an analyte in the liquid sample, the fourth processor configured to be responsive to a request to disable the second power supply to provide a corresponding message to the second processor,

wherein the second processor is configured to cease storing information in the outbound buffer of the memory device when the fourth processor produces the corresponding message so that the memory device does not reset the timer circuit before the predefined time period elapses since last resetting the timer circuit and the memory device then disables the second power supply such that the second power supply does not produce the second supply voltage.

40. The electronic device of claim 16 wherein the second power supply is always enabled such that the second power supply always produces the second supply voltage,

and wherein the first processor is configured to be responsive to a number of different events to transition into, and out of, a number of different low power states.

41. The electronic device of claim 40 wherein the first processor further comprises a timer circuit,

and wherein the first processor is configured to remain in a fully powered awake state as long as a first predefined time period does not elapse since last resetting the timer circuit,

42. The electronic device of claim 41 wherein the memory device comprises an outbound buffer that is configured to store therein information sent to the memory device by the second processor that is to be communicated wirelessly to the another electronic device by the first processor, the outbound buffer being in data communication with the first and second processors,

wherein the first processor is configured to periodically check a status of the outbound buffer and to reset the timer circuit only if the outbound buffer contains information to be wirelessly communicated to the another electronic device,

and wherein the first processor is configured to transition to a first low power state if the first predefined time period elapses since last resetting the timer circuit, the first processor consuming less electrical power in the first low power state than when in the fully powered awake state.

43. The electronic device of claim 42 wherein the first processor is configured to transition to a second low power state, in which the first processor consumes less electrical power than when in the first low power state, if a second predefined time period elapses since last resetting the timer circuit, the second predefined time period being greater than the first predefined time period.

44. The electronic device of claim 42 wherein the first processor is configured to transition to successively lower power states, in which the first processor consumes successively less power than in the previous low power state, as the time period that elapses since resetting the timer circuit successively increases beyond the first predefined time period.

45. The electronic device of claim 44 wherein the first processor is configured in a lowest power state only to periodically wake up to check the status of the outbound buffer of the memory device, and to wake up to the fully powered awake state if the outbound buffer of the memory device has information stored therein, the first processor otherwise configured to transition back to the lowest power state.

46. The electronic device of claim 40 further comprising an on/off switch,

wherein the first processor is configured to transition from any of the number of different low power states to a fully powered awake state when the on/off switch is switched to an on position.

47. The electronic device of claim 46 wherein the first processor is configured to transition from the fully powered awake state and any of the number of different low power states to a lowest power sleep state when the on/off switch is switched to an off position.

48. The electronic device of claim 46 wherein the memory device has a sleep state and an awake state,

and wherein the memory device is configured to transition from the sleep state of the memory device to the awake state of the memory device when the on/off switch is switched to the on position.

49. The electronic device of claim 45 further comprising:

a test element receiving port configured to receive a test element,

electronic circuitry configured to detect insertion of the test element into the test element receiving port and to produce a corresponding strip insert signal,

a fourth processor configured to analyze a liquid sample provided on the test element to determine a concentration of an analyte in the liquid sample, the fourth processor configured to be responsive to the strip insert signal to provide a corresponding strip insert message to the second processor,

wherein the second processor is configured to cease storing information in the outbound buffer of the memory device when the fourth processor produces the strip insert message so that the first processor then successively transitions to lower power states as successively longer time periods elapse since last resetting the timer circuit.

50. The electronic device of claim 49 wherein the fourth processor is configured to provide a test complete message when the fourth processor has determined the concentration of an analyte in the liquid sample,

and wherein the second processor is configured to resume storing information in the outbound buffer of the memory device when the fourth processor produces the test complete message so that the first processor then transitions to the fully powered awake state to service the information stored in the outbound buffer of the memory device.

51. The electronic device of claim 40 further comprising a plurality of user activated buttons or keys,

wherein the first processor is configured to transition from any of the number of different low power states to a fully powered awake state upon detection of one of a simultaneous activation of a predefined combination of two or more of the plurality of user activated buttons or keys, activation of a predefined sequence of two or more of the plurality of user activated buttons or keys and a dedicated one of the plurality of user activated buttons or keys.

52. The electronic device of claim 40 further comprising a plurality of user activated buttons or keys,

wherein the first processor is configured to transition from the fully powered awake state and any of the number of different low power states to an un-powered off state upon detection of one of a simultaneous activation of a predefined combination of two or more of the plurality of user activated buttons or keys, activation of a predefined sequence of two or more of the plurality of user activated buttons or keys and a dedicated one of the plurality of user activated buttons or keys.

53. The electronic device of claim 16 further comprising a clock circuit having a programming input that is electrically connected to the second processor and an output that is electrically connected to the memory device,

wherein the clock circuit is programmable via the second processor with at least one automatic on time or reminder, and the clock circuit is configured to produce a trigger signal upon occurrence of the at least one automatic on time or reminder,

and wherein the memory device is responsive to the trigger signal, when the second power supply is disabled, to enable the second power supply such that the second power supply produces the second supply voltage.

54. The electronic device of claim 16 further comprising:

a test element receiving port configured to receive a test element,

a fourth processor that is electrically connected to the second processor and that is configured to analyze a liquid sample provided on the test element to determine a concentration of an analyte in the liquid sample, the fourth processor configured to provide a value of the concentration of the analyte in the liquid sample to the second processor, and

an electronic switch configured to produce a first signal upon detection of insertion of the test element into the test element receiving port and to produce a second signal upon detection of removal of the test element from the test element receiving port, the electronic switch having an output that is electrically connected to the fourth processor and to the memory device such that the first and second signals produced by the switch are provided to the fourth processor and to the memory device,

wherein the memory device configured to be responsive to the first signal produced by the electronic switch to command orderly shutdown of the first processor and to then disable the second power supply such that the second power supply does not produce the second supply voltage.

55. The electronic device of claim 54 wherein the memory device is configured to be responsive to the second signal produced by the electronic switch, if the second power supply is disabled, to enable the second power supply such that the second power supply produces the second supply voltage.

56. The electronic device of claim 16 further comprising:

a test element receiving port configured to receive a test element, and

a switch configured to produce a first signal upon detection of insertion of the test element into the test element receiving port and to produce a second signal upon detection of removal of the test element from the test element receiving port, the switch having an output that is electrically connected only to the memory device such that the first and second signals produced by the switch are provided to the memory device,

wherein the memory device configured to be responsive to the first signal produced by the switch to command orderly shutdown of the first processor and to then disable the second power supply such that the second power supply does not produce the second supply voltage.

57. The electronic device of claim 55 wherein the memory device is configured to be responsive to the second signal produced by the switch, if the second power supply is disabled, to enable the second power supply such that the second power supply produces the second supply voltage.

58. The electronic device of claim 16 further comprising a current sensing circuit having at least one input that is electrically connected to the first power supply and an output that is electrically connected to the second power supply, the current sensing circuit configured to produce a control signal having a first state and a second state based on a magnitude of a supply current produced by the first power supply,

wherein the first state of the control signal produced by the current sensing circuit disables the second power supply such that the second power supply does not produce the second supply voltage and the second state of the control signal produced by the current sensing circuit enables the second power supply such that the second power supply produces the second supply voltage.

59. The electronic device of claim 58 wherein the current sensing circuit is configured to produce the second state of the control signal when the second processor is fully activated for operation such that the magnitude of the supply current produced by the first power supply is greater than when the second processor is not fully activated for operation.

60. The electronic device of claim 59 wherein the second processor includes a timer circuit that the second processor resets periodically when the second processor is actively operating,

and wherein the second processor is configured to transition to a low power sleep state if the second processor is inactive for a predefined time period following a last reset of the timer circuit,

and wherein the current sensing circuit is configured to produce the first state of the control signal when the second processor transitions to the low power sleep state such that the magnitude of the supply current produced by the first power supply is greater than when the second processor is actively operating.

61. The electronic device of claim 58 further comprising:

a test element receiving port configured to receive a test element,

electronic circuitry, and

a fourth processor electrically connected to the electronic circuitry and to the second processor,

wherein the first power supply provides the first supply voltage to the electronic circuitry and to the fourth processor,

and wherein the electronic circuitry and the fourth processor are each normally in a low power sleep state such that the magnitude of the supply current produced by the first power supply is less than when the electronic circuitry and the fourth processor are both actively operating,

and wherein the current sensing circuit normally produces the second state of the control signal, such that the second power supply is normally enabled and producing the second supply voltage, when the electronic circuitry and the fourth processor are each in the low power sleep states.

62. The electronic device of claim 61 wherein the electronic circuitry is configured to be responsive to insertion of the test element into the test element receiving port to transition from the low power sleep state thereof to an actively operating state and produce a corresponding strip insert signal,

and wherein the fourth processor is configured to be responsive to the strip insert signal to transition from the low power operating state thereof to an actively operating state and analyze a liquid sample provided on the test element to determine a concentration of an analyte in the liquid sample,

and wherein the magnitude of the supply current produced by the first power supply when the electronic circuitry and the fourth processor are both actively operating is greater than when the electronic circuitry and the fourth processor are in their low power sleep states,

and wherein the current sensing circuit is configured to transition the control signal from the first state thereof to the second state thereof when the electronic circuitry and the fourth processor each transition from the low power sleep state to the actively operating state.

63. The electronic device of claim 62 wherein the electronic circuitry and the fourth processor are each configured to transition from the actively operating state to the low power sleep state after the fourth processor determines the concentration of the analyte in the liquid sample,

and wherein the current sensing circuit is configured to transition the control signal from the second state thereof to the first state thereof when the electronic circuitry and the fourth processor each transition from the actively operating state to the low power sleep state after the fourth processor determines the concentration of the analyte in the liquid sample.

64. The electronic device of claim 61 wherein the electronic circuitry comprises a timer circuit that is programmed with at least one automatic on time or reminder, and the clock circuit is configured to produce a trigger signal upon occurrence of the at least one automatic on time or reminder, and the electronic circuitry is configured to be responsive to the trigger signal to transition from the low power operating state thereof to an actively operating state and to pass the trigger signal to the fourth processor,

and wherein the fourth processor is configured to be responsive to the trigger signal to transition from the low power operating state thereof to an actively operating state and to pass the trigger signal to the second processor,

and wherein the magnitude of the supply current produced by the first power supply when the electronic circuitry and the fourth processor are both actively operating is greater than when the electronic circuitry and the fourth processor are in their low power sleep states,

and wherein the current sensing circuit is configured to transition the control signal from the first state thereof to the second state thereof when the electronic circuitry and the fourth processor each transition from the low power sleep state to the actively operating state.

65. The electronic device of claim 16 further comprising a current sensing circuit having at least one input that is electrically connected to the first power supply and an output that is electrically connected to the memory device, the current sensing circuit configured to produce a control signal having a first state and a second state based on a magnitude of a supply current produced by the first power supply,

wherein the memory device is responsive to the first state of the control signal produced by the current sensing circuit to disable the second power supply such that the second power supply does not produce the second supply voltage, and to the second state of the control signal produced by the current sensing circuit to enable the second power supply such that the second power supply produces the second supply voltage.

66. The electronic device of claim 65 wherein the current sensing circuit is configured to produce the second state of the control signal when the second processor is fully activated for operation such that the magnitude of the supply current produced by the first power supply is greater than when the second processor is not fully activated for operation.

67. The electronic device of claim 66 wherein the second processor includes a timer circuit that the second processor resets periodically when the second processor is actively operating,

and wherein the second processor is configured to transition to a low power sleep state if the second processor is inactive for a predefined time period following a last reset of the timer circuit,

and wherein the current sensing circuit is configured to produce the first state of the control signal when the second processor transitions to the low power sleep state such that the magnitude of the supply current produced by the first power supply is greater than when the second processor is actively operating.

68. The electronic device of claim 65 further comprising:

a test element receiving port configured to receive a test element,

electronic circuitry, and

a fourth processor electrically connected to the electronic circuitry and to the second processor,

wherein the first power supply provides the first supply voltage to the electronic circuitry and to the fourth processor,

and wherein the electronic circuitry and the fourth processor are each normally in a low power sleep state such that the magnitude of the supply current produced by the first power supply is less than when the electronic circuitry and the fourth processor are both actively operating,

and wherein the current sensing circuit normally produces the second state of the control signal, such that the second power supply is normally enabled and producing the second supply voltage, when the electronic circuitry and the fourth processor are each in the low power sleep states.

69. The electronic device of claim 68 wherein the electronic circuitry is configured to be responsive to insertion of the test element into the test element receiving port to transition from the low power sleep state thereof to an actively operating state and produce a corresponding strip insert signal,

and wherein the fourth processor is configured to be responsive to the strip insert signal to transition from the low power operating state thereof to an actively operating state and analyze a liquid sample provided on the test element to determine a concentration of an analyte in the liquid sample,

and wherein the magnitude of the supply current produced by the first power supply when the electronic circuitry and the fourth processor are both actively operating is greater than when the electronic circuitry and the fourth processor are in their low power sleep states,

and wherein the current sensing circuit is configured to transition the control signal from the first state thereof to the second state thereof when the electronic circuitry and the fourth processor each transition from the low power sleep state to the actively operating state.

70. The electronic device of claim 69 wherein the electronic circuitry and the fourth processor are each configured to transition from the actively operating state to the low power sleep state after the fourth processor determines the concentration of the analyte in the liquid sample,

and wherein the current sensing circuit is configured to transition the control signal from the second state thereof to the first state thereof when the electronic circuitry and the fourth processor each transition from the actively operating state to the low power sleep state after the fourth processor determines the concentration of the analyte in the liquid sample.

71. The electronic device of claim 68 wherein the electronic circuitry comprises a timer circuit that is programmed with at least one automatic on time or reminder, and the clock circuit is configured to produce a trigger signal upon occurrence of the at least one automatic on time or reminder, and the electronic circuitry is configured to be responsive to the trigger signal to transition from the low power operating state thereof to an actively operating state and to pass the trigger signal to the fourth processor,

and wherein the fourth processor is configured to be responsive to the trigger signal to transition from the low power operating state thereof to an actively operating state and to pass the trigger signal to the second processor,

and wherein the magnitude of the supply current produced by the first power supply when the electronic circuitry and the fourth processor are both actively operating is greater than when the electronic circuitry and the fourth processor are in their low power sleep states,

and wherein the current sensing circuit is configured to transition the control signal from the first state thereof to the second state thereof when the electronic circuitry and the fourth processor each transition from the low power sleep state to the actively operating state.

72. The electronic device of claim 42 wherein, if a wireless connection between the electronic device and the another electronic device is terminated or lost and the second processor sends information to the outbound buffer, one of the first processor and the second processor is configured to clear the outbound buffer after a predefined number of failed attempts by the first processor to reestablish a wireless connection between the electronic device and the another electronic device.

73. The electronic device of claim 72 wherein the first processor is configured to transition to successively lower power states, in which the first processor consumes successively less power than in the previous low power state, as the time period that elapses since resetting the timer circuit successively increases beyond the first predefined time period following the predefined number of failed attempts by the first processor to reestablish a wireless connection between the electronic device and the another electronic device.

74. The electronic device of claim 73 wherein the first processor is configured in a lowest power state only to periodically wake up to check the status of the outbound buffer of the memory device, and to wake up to the fully powered awake state if the outbound buffer of the memory device has information stored therein, the first processor otherwise configured to transition back to the lowest power state.

75. The electronic device of claim 74 wherein the first processor is configured in the lowest power state to produce a power supply control signal if the time period that elapses since resetting the timer circuit reaches a predefined time out value that is greater than the time period for which the first processor enters the lowest power sleep state,

and wherein the second power supply is configured to become disabled such that the second power supply does not produce the second supply voltage when the first processor produces the power supply control signal.

76. The electronic device of claim 75 further comprising a plurality of user activated buttons or keys,

wherein the second power supply is configured to be responsive to one of a simultaneous activation of a predefined combination of two or more of the plurality of user activated buttons or keys, activation of a predefined sequence of two or more of the plurality of user activated buttons or keys and a dedicated one of the plurality of user activated buttons or keys to become enabled such that the second power supply produces the second supply voltage,

and wherein the first processor is configured to enter the lowest power sleep state when the second power supply is via the one of the predefined combination of two or more of the plurality of user activated buttons or keys, activation of a predefined sequence of two or more of the plurality of user activated buttons or keys and a dedicated one of the plurality of user activated buttons or keys.

77. The electronic device of claim 44 wherein the first processor is configured in the lowest power state to produce a power supply control signal if the time period that elapses since resetting the timer circuit reaches a predefined time out value that is greater than the time period for which the first processor enters the lowest power sleep state,

and wherein the second power supply is configured to become disabled such that the second power supply does not produce the second supply voltage when the first processor produces the power supply control signal.

78. The electronic device of claim 77 further comprising a plurality of user activated buttons or keys,

wherein the second power supply is configured to be responsive to one of a simultaneous activation of a predefined combination of two or more of the plurality of user activated buttons or keys, activation of a predefined sequence of two or more of the plurality of user activated buttons or keys and a dedicated one of the plurality of user activated buttons or keys to become enabled such that the second power supply produces the second supply voltage,

and wherein the first processor is configured to enter the lowest power sleep state when the second power supply is via the one of the predefined combination of two or more of the plurality of user activated buttons or keys, activation of a predefined sequence of two or more of the plurality of user activated buttons or keys and a dedicated one of the plurality of user activated buttons or keys.

79. An electronic device for communicating wirelessly with another electronic device, the electronic device comprising:

a first processor configured to control only wireless communications with the another device but not operations associated only with the electronic device,

a second processor configured to control the operations associated only with the electronic device but not the wireless communications with the another device,

a memory device electrically connected to the first and second processors, and

a clock circuit that is separate and independent from the first and second processors and that produces at least one timing signal that controls exchange of the information between the first and second processors and the memory device.

80. An electronic device for communicating wirelessly with another electronic device, the electronic device comprising:

a first processor that controls only wireless communications with the another device and excluding operations associated only with the electronic device,

a second processor that controls the operations associated only with the electronic device and excluding the wireless communications with the another device, and

a memory device connected between the first and second processors, the first and second processors each operate autonomously with respect to each other and each exchange information with the memory device independently of each other.

81. An electronic device for communicating wirelessly with another electronic device, the electronic device comprising:

a first processor that controls only wireless communications with the another device and excluding operations associated only with the electronic device,

a second processor that controls the operations associated only with the electronic device and excluding the wireless communications with the another device, and

a memory device connected between the first and second processors, the first and second processors each operate independently of each other and each operate asynchronously with respect to each other when exchanging information with the memory device.