NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
First Claim
1. A non-volatile semiconductor memory device, comprising:
- a memory cell array having a plurality of non-volatile memory cells capable electrically rewriting data, bit lines and source lines;
a driver circuit coupled with the source lines of the memory cell array, to output a voltage higher than a power source voltage or a programming voltage for writing data in a memory cell at an output terminal and discharge the source lines to ground by switching over; and
a sense amplifier circuit coupled with the bit line to read data in the memory cell, the sense amplifier circuit including a sense node and a capacitor having a first terminal coupled with the sense node and a second terminal to receive a plurality of voltages to boost the sense node.
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Accused Products
Abstract
A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells capable electrically rewriting data, bit lines and source lines. A driver circuit is coupled with the source lines of the memory cell array to output a voltage higher than a power source voltage or a programming voltage for writing data in the memory cell by switching over, and the driver circuit discharges the source lines to ground. A sense amplifier circuit is coupled with the bit line and reads out the data in the memory cell. The sense amplifier includes a sense node and a capacitor having first and second terminals, and the first terminal is coupled with the sense node. The sense node is boosted by a plurality of voltages applied to the second terminal of the capacitor.
25 Citations
15 Claims
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1. A non-volatile semiconductor memory device, comprising:
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a memory cell array having a plurality of non-volatile memory cells capable electrically rewriting data, bit lines and source lines; a driver circuit coupled with the source lines of the memory cell array, to output a voltage higher than a power source voltage or a programming voltage for writing data in a memory cell at an output terminal and discharge the source lines to ground by switching over; and a sense amplifier circuit coupled with the bit line to read data in the memory cell, the sense amplifier circuit including a sense node and a capacitor having a first terminal coupled with the sense node and a second terminal to receive a plurality of voltages to boost the sense node. - View Dependent Claims (2, 3, 4)
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5. A non-volatile semiconductor memory device, comprising:
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a memory cell array including a plurality of NAND strings arranged in a matrix, each of the NAND strings having a plurality of non-volatile memory cells connected in series and capable electrically rewriting data, and first and second selection gate transistors coupled with both ends of the plurality of non-volatile memory cells; source lines coupled with the first selection transistors of the NAND strings; bit lines coupled with the second selection transistors of the NAND strings; a source driver circuit coupled with the source line to supply a higher voltage than a power source voltage; and a sense amplifier circuit coupled with the bit line to read data in the memory cell; and wherein the sense amplifier circuit further includes sense node, a capacitor having a first terminal coupled with the sense node and a second terminal to receive a plurality of voltages to boost the sense node, and a first transistor connected between the sense node and the bit line of the memory cell array, and the first transistor is switched depending on the voltage of the bit line. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification