MEMORY KINK CHECKING
First Claim
1. A method for operating a memory device, comprising:
- selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line;
determining an effect on a second data line due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line; and
applying kink correction to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.
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Accused Products
Abstract
This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.
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Citations
55 Claims
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1. A method for operating a memory device, comprising:
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selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line; determining an effect on a second data line due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line; and applying kink correction to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for operating a memory device, comprising:
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performing a first kink check before applying a programming pulse including; floating first data lines and selectively applying one of a plurality of voltages to second data lines, wherein the voltage applied to a respective one of the second data lines is dependent upon a programming status of a memory cell coupled to that second data line and to an access line, wherein a plurality of memory cells coupled to the access line are alternately associated with a respective one of the first data lines and the second data lines; and sensing the first data lines; and performing a second kink check before applying the programming pulse including; floating the second data lines and selectively applying one of the plurality of voltages to the first data lines, wherein the voltage applied to a respective one of the first data lines is dependent upon a programming status of a memory cell of the plurality of memory cells that is coupled to that first data line and to the access line; and sensing the second data lines. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A method for operating a memory device, comprising:
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determining a number memory cells coupled to a common access line and adjacent to a first memory cell that will be program inhibited during a subsequent programming pulse, wherein the first memory cell is associated with a first data line; wherein the determining includes; applying a first voltage to a second data line when a second memory cell that is adjacent to the first memory cell and associated with the second data line has completed programming; applying a second voltage to the second data line when the second memory cell has not completed programming; and determining an effect on the first data line due at least in part to a capacitive coupling between at least the first data line and the second data line; and applying kink correction to the first data line according to the number of memory cells coupled to the common access line and adjacent to the first memory cell that will be program inhibited during the subsequent programming pulse. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method for operating a memory device, comprising:
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floating a first data line; applying a first voltage to a second data line if a memory cell coupled to the second data line and to a selected access line has completed programming; applying a second voltage to the second data line if the memory cell coupled to the second data line and to the selected access line has not completed programming; and sensing an effect on the first data line due at least in part to a capacitive coupling between at least the first data line and the second data line; floating the second data line; applying the first voltage to the first data line if the memory cell coupled to the first data line and to the selected access line has completed programming; applying the second voltage to the first data line if the memory cell coupled to the first data lien and to the selected access line has not completed programming; sensing an effect on the second data line due at least in part to a capacitive coupling between at least the second data line and the first data line; applying kink correction to the first data line according to the effect sensed on the first data line; and applying kink correction to the second data line according to the effect sensed on the second data line.
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32. A memory device, comprising:
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a first data line associated with a first memory cell and a first control element; a second data line associated with a second memory cell and a second control element, wherein the second memory cell is adjacent to the first memory cell; wherein the first control element is configured to; apply a first voltage to the first data line if the first memory cell has completed programming; and apply a second voltage to the first data line if the first memory cell has not completed programming; and wherein the second control element is configured to determine an effect of the application of the voltage on the first data line on the second data line due at least in part to a capacitive coupling. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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49. A memory device, comprising:
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memory cells coupled to an access line; data lines, each associated with a respective one of the memory cells; control elements, each associated with a respective one of the data lines; wherein; a first number of the control elements are configured to; float a first number of the data lines coupled to the first number of control elements; sense voltages on the first number of data lines due at least in part to voltages applied to the second number of data lines and capacitive coupling therewith; and selectively apply one of a plurality of voltages to the first number of data lines; a second number of the control elements are configured to; selectively apply one of the plurality of voltages to a second number of the data lines coupled to the second number of control elements; float the second number of data lines; and sense voltages on the second number of data lines due at least in part to voltages applied to the first data lines and capacitive coupling therewith. - View Dependent Claims (50, 51, 52, 53, 54, 55)
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Specification