MEMORY KINK CHECKING

• US 20110063919A1
• Filed: 09/14/2009
• Published: 03/17/2011
• Est. Priority Date: 09/14/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chandrasekhar, Uday, Helm, Mark
• Granted Patent: US 8,482,975 B2
• Time in Patent Office: Days
• US Class Current: 365/185.19
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.

Claims

1. A method for operating a memory device, comprising:

selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line;

determining an effect on a second data line due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line; and

applying kink correction to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.

2. The method of claim 1, wherein the method includes floating the second data line while applying the one of the plurality of voltages.

3. The method of claim 1, wherein the method includes:

selectively applying one of the plurality of voltages to a third data line according to a programming status of a third memory cell, wherein the third data line is coupled to the third memory cell, the third memory cell is adjacent to the second memory cell, and the third memory cell is coupled to the selected access line; and

determining an effect on the second data line due at least in part to the voltage applied to the first data line and the voltage applied to the third data line.

4. The method of claim 1, wherein determining the effect on the second data line includes sensing a voltage on the second data line, wherein the voltage on the second data line is determined at least in part by the voltage applied to the first data line.

5. The method of claim 1, wherein determining the effect on the second data line includes determining the effect while the one of the plurality of voltages is applied to the first data line.

6. The method of claim 1, wherein the programming status is selected from the group of programming statuses including programming complete and programming incomplete.

7. The method of claim 1, wherein selectively applying one of the plurality of voltages includes:

applying a first kink check voltage when the programming status of the first memory cell is programming incomplete; and

applying a second kink check voltage when the programming status of the first memory cell is programming complete.

8. The method of claim 1, wherein applying kink correction to the second data line includes applying a kink correction voltage to the second data line.

9. The method of claim 8, wherein applying the kink correction voltage includes applying a voltage having a magnitude corresponding to a voltage sensed on the second data line.

10. The method of claim 9, wherein applying the kink correction voltage includes applying a voltage having a magnitude proportional to the voltage sensed on the second data line.

11. A method for operating a memory device, comprising:

performing a first kink check before applying a programming pulse including;

floating first data lines and selectively applying one of a plurality of voltages to second data lines, wherein the voltage applied to a respective one of the second data lines is dependent upon a programming status of a memory cell coupled to that second data line and to an access line, wherein a plurality of memory cells coupled to the access line are alternately associated with a respective one of the first data lines and the second data lines; and

sensing the first data lines; and

performing a second kink check before applying the programming pulse including;

floating the second data lines and selectively applying one of the plurality of voltages to the first data lines, wherein the voltage applied to a respective one of the first data lines is dependent upon a programming status of a memory cell of the plurality of memory cells that is coupled to that first data line and to the access line; and

sensing the second data lines.

12. The method of claim 11, wherein sensing the second data lines includes sensing the second data lines for kink.

13. The method of claim 11, wherein selectively applying one of the plurality of voltages to the data lines includes:

applying a first voltage when the programming status of the respective memory cell is complete programming; and

applying a second voltage when the programming status of the respective memory cell is incomplete programming.

14. The method of claim 11, wherein sensing the first data lines includes sensing a voltage on the first data lines due at least in part to capacitive coupling with adjacent second data lines each having one of the plurality of voltages applied thereto.

15. The method of claim 11, wherein sensing the second data lines includes sensing a voltage on the second data lines due at least in part to capacitive coupling with adjacent first data lines each having one of the plurality of voltages applied thereto.

16. The method of claim 11, wherein the method includes applying the programming pulse to the access line while applying kink correction to at least one of the data lines, wherein the kink correction applied to the at least one of the data lines is based at least in part on the sensing of the at least one of the data lines.

17. The method of claim 16, wherein the method includes applying the programming pulse simultaneously to the memory cells coupled to:

the access line;

the first data lines; and

the second data lines.

18. The method of claim 16, wherein applying kink correction includes applying a voltage to the at least one of the data lines corresponding to a voltage sensed on the at least one of the data lines.

19. The method of claim 11, wherein the method includes performing the first and the second kink check before every programming pulse.

20. A method for operating a memory device, comprising:

determining a number memory cells coupled to a common access line and adjacent to a first memory cell that will be program inhibited during a subsequent programming pulse, wherein the first memory cell is associated with a first data line;

wherein the determining includes;

applying a first voltage to a second data line when a second memory cell that is adjacent to the first memory cell and associated with the second data line has completed programming;

applying a second voltage to the second data line when the second memory cell has not completed programming; and

determining an effect on the first data line due at least in part to a capacitive coupling between at least the first data line and the second data line; and

applying kink correction to the first data line according to the number of memory cells coupled to the common access line and adjacent to the first memory cell that will be program inhibited during the subsequent programming pulse.

21. The method of claim 20, wherein determining the effect on the first data line includes:

sensing a first voltage when the number of memory cells coupled to the common access line and adjacent to the first memory cell that will be program inhibited during the subsequent programming pulse is zero;

sensing a second voltage when the number of memory cells is one; and

sensing a third voltage when the number of memory cells is two.

22. The method of claim 20, wherein applying kink correction includes applying the kink correction during the subsequent programming pulse.

23. The method of claim 20, wherein applying the kink correction includes increasing a voltage that is applied to the particular data line during a programming pulse.

24. The method of claim 23, wherein applying kink correction includes increasing the voltage that is applied to the first data line beyond an increase in voltage that is applied as part of a selective slow programming convergence (SSPC) technique.

25. The method of claim 20, wherein applying kink correction includes:

applying a first kink correction to the first data line when the number of memory cells coupled to the common access line and adjacent to the first memory cell that will be program inhibited during the subsequent programming pulse is one; and

applying a second kink correction to the first data line when the number of memory cells is two.

26. The method of claim 25, wherein a magnitude of the second kink correction is twice as large as a magnitude of the first kink correction.

27. The method of claim 25, wherein a magnitude of the second kink correction is equal to a magnitude of the first kink correction.

28. The method of claim 20, wherein applying kink correction according to the number of memory cells coupled to the common access line and adjacent to the first memory cell that will be program inhibited during the subsequent programming pulse includes applying no kink correction when the number of memory cells coupled to the common access line and adjacent to the first memory cell that will be program inhibited during the subsequent programming pulse is zero.

29. The method of claim 20, wherein determining the number of memory cells coupled to the common access line and adjacent to a first memory cell that will be program inhibited during a subsequent programming pulse includes determining the number of memory cells between programming pulses of a programming operation.

30. The method of claim 20, wherein determining the number of memory cells coupled to the common access line and adjacent to the first memory cell that will be program inhibited during a subsequent programming operation includes determining the number of memory cells before each programming pulse.

31. A method for operating a memory device, comprising:

floating a first data line;

applying a first voltage to a second data line if a memory cell coupled to the second data line and to a selected access line has completed programming;

applying a second voltage to the second data line if the memory cell coupled to the second data line and to the selected access line has not completed programming; and

sensing an effect on the first data line due at least in part to a capacitive coupling between at least the first data line and the second data line;

floating the second data line;

applying the first voltage to the first data line if the memory cell coupled to the first data line and to the selected access line has completed programming;

applying the second voltage to the first data line if the memory cell coupled to the first data lien and to the selected access line has not completed programming;

sensing an effect on the second data line due at least in part to a capacitive coupling between at least the second data line and the first data line;

applying kink correction to the first data line according to the effect sensed on the first data line; and

applying kink correction to the second data line according to the effect sensed on the second data line.

32. A memory device, comprising:

a first data line associated with a first memory cell and a first control element;

a second data line associated with a second memory cell and a second control element, wherein the second memory cell is adjacent to the first memory cell;

wherein the first control element is configured to;

apply a first voltage to the first data line if the first memory cell has completed programming; and

apply a second voltage to the first data line if the first memory cell has not completed programming; and

wherein the second control element is configured to determine an effect of the application of the voltage on the first data line on the second data line due at least in part to a capacitive coupling.

33. The device of claim 32, wherein the device includes a third data line associated with a third memory cell and a third control element, wherein the third memory cell is adjacent to the second memory cell;

wherein the third control element is configured to;

apply the first voltage to the third data line if the third memory cell has completed programming; and

apply the second voltage to the third data line if the third memory cell has not completed programming; and

wherein the second control element is configured to determine an effect of the application of the voltage on the third data line on the second data line due at least in part to a capacitive coupling.

34. The device of claim 32, wherein the second control element is configured to float the second data line during application of the voltage to the first data line.

35. The device of claim 32, wherein the second control element being configured to determine the effect comprises the second control element being configured to sense a voltage on the second data line due at least in part to the capacitive coupling, wherein the capacitive coupling is between at least the first data line and the second data line.

36. The device of claim 32, wherein the second control element is configured to apply a kink correction voltage to the second data line during a programming operation of the second memory cell according to the determined effect.

37. The device of claim 36, wherein the kink correction voltage comprises a voltage substantially equivalent to an increase in voltage applied to a control gate of the second memory cell during a programming pulse thereon due at least in part to capacitive coupling between at least the first data line and the second data line.

38. The device of claim 32, wherein:

the second control element includes a number of decoded storage elements; and

the second control element is configured to select one of the number of decoded storage elements to apply a corresponding voltage to the second data line during a programming pulse.

39. The device of claim 38, wherein the corresponding voltage is selected from the group of corresponding voltages including:

zero volts;

½

kink correction voltage;

kink correction voltage;

selective slow programming convergence (SSPC) voltage;

SSPC voltage+½

kink correction voltage;

SSPC voltage+kink correction voltage; and

inhibit voltage.

40. The device of claim 32, wherein:

the second control element includes a number of encoded storage elements; and

the second control element is configured to select a combination of the number of encoded storage elements to apply a corresponding voltage to the second data line during a programming pulse.

41. The device of claim 32, wherein the second control element is located on an opposite side of the memory device from the first control element.

42. The device of claim 32, wherein the second control element is coupled to an opposite end of the second data line with respect to an end of the first data line to which the first control element is coupled.

43. The device of claim 32, wherein:

the second control element includes five decoded storage elements; and

the second control element is configured to select one of the five decoded storage elements to apply a corresponding voltage to the second data line during a programming pulse.

44. The device of claim 43, wherein the corresponding voltage is selected from the group of corresponding voltages including:

zero volts;

kink correction voltage;

selective slow programming convergence (SSPC) voltage;

SSPC voltage+kink correction voltage; and

inhibit voltage.

45. The device of claim 32, wherein the first data line is a first bit line and wherein the second data line is a second bit line.

46. The device of claim 32, wherein the first control element and the second control element include and/or are coupled to control circuitry.

47. The device of claim 46, wherein the control circuitry includes sensing circuitry selectively coupled to a respective data line by a first switching device, wherein the sensing circuitry includes:

a temporary data cache (tdc) node selectively coupled to precharging circuitry by a second switching device;

the tdc node selectively coupled to a latch by a third switching device; and

the tdc node coupled to a capacitance.

48. The device of claim 47, wherein the capacitance is:

selectively coupled to ground by a fourth switching device;

selectively coupled to boosting circuitry by a fifth switching device; and

selectively coupled in series with another capacitance to ground by a sixth switching device.

49. A memory device, comprising:

memory cells coupled to an access line;

data lines, each associated with a respective one of the memory cells;

control elements, each associated with a respective one of the data lines;

wherein;

a first number of the control elements are configured to;

float a first number of the data lines coupled to the first number of control elements;

sense voltages on the first number of data lines due at least in part to voltages applied to the second number of data lines and capacitive coupling therewith; and

selectively apply one of a plurality of voltages to the first number of data lines;

a second number of the control elements are configured to;

selectively apply one of the plurality of voltages to a second number of the data lines coupled to the second number of control elements;

float the second number of data lines; and

sense voltages on the second number of data lines due at least in part to voltages applied to the first data lines and capacitive coupling therewith.

50. The device of claim 49, wherein:

the first number of control elements are configured to selectively apply kink correction to the first number of data lines according to the voltages sensed on the first number of data lines during a programming pulse applied to the selected access line; and

the second number of control elements are configured to selectively apply kink correction to the second number of data lines according to the voltages sensed on the second number of data lines during the programming pulse applied to the selected access line.

51. The device of claim 49, wherein the second number of control elements are coupled to the second number of data lines on an opposite side of the memory cells with respect to a side of the memory cells on which the first number of control elements are coupled to the first number of data lines.

52. The device of claim 49, wherein the second number of control elements are coupled to the second number of data lines on a same side of the memory cells as the side on which the first number of control elements are coupled to the first number of data lines.

53. The device of claim 49, wherein the first number of control elements do not share a tangible physical connection with the second number of control elements.

54. The device of claim 49, wherein the control elements each include a cache element configured to store a programming status associated with the respective one of the memory cells associated with the respective one of the data lines associated with each control element, wherein the programming status is selected from the group of programming statuses including programming complete and programming incomplete.

55. The device of claim 54, wherein each control element is configured to update the programming status stored in each cache element in response to a program verify operation performed after a programming pulse on the respective one of the memory cells associated with the respective one of the data lines associated with each control element.