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INTERFACES, CIRCUITS, AND METHODS FOR COMMUNICATING WITH A DOUBLE DATA RATE MEMORY DEVICE

  • US 20110063931A1
  • Filed: 09/11/2009
  • Published: 03/17/2011
  • Est. Priority Date: 09/11/2009
  • Status: Active Grant
First Claim
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1. An input/output interface for communicating between an application specific integrated circuit (ASIC) with a memory controller and a double data rate (DDR) memory device, the interface comprising:

  • a strobe circuit comprising;

    a preamble logic element arranged to receive strobe signals from the DDR memory device and generate a preamble signal;

    a first counter arranged to receive the preamble signal and the strobe signals, the first counter generating a strobe count signal;

    a second counter arranged to receive a read enable signal and an ASIC-generated clock, the second counter generating a read count signal;

    a strobe park circuit arranged to receive the preamble signal, the read count signal and the strobe count signal, the strobe park circuit generating a control signal that controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when the ASIC is not receiving data from the DDR memory device; and

    a first synchronizer arranged to receive the ASIC-generated clock and generate a synchronized count in response to a reset signal from the memory controller; and

    a data circuit comprising;

    a FIFO buffer arranged to receive a data input from the DDR memory device, the strobe signals, and the strobe count signal, the HFO buffer generating a read data signal; and

    a second synchronizer arranged to receive the read data signal, the ASIC-generated clock, and the synchronized count, the second synchronizer generating a representation of the read data signal in synchronization with the ASIC-generated clock.

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