INTERFACES, CIRCUITS, AND METHODS FOR COMMUNICATING WITH A DOUBLE DATA RATE MEMORY DEVICE
First Claim
1. An input/output interface for communicating between an application specific integrated circuit (ASIC) with a memory controller and a double data rate (DDR) memory device, the interface comprising:
- a strobe circuit comprising;
a preamble logic element arranged to receive strobe signals from the DDR memory device and generate a preamble signal;
a first counter arranged to receive the preamble signal and the strobe signals, the first counter generating a strobe count signal;
a second counter arranged to receive a read enable signal and an ASIC-generated clock, the second counter generating a read count signal;
a strobe park circuit arranged to receive the preamble signal, the read count signal and the strobe count signal, the strobe park circuit generating a control signal that controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when the ASIC is not receiving data from the DDR memory device; and
a first synchronizer arranged to receive the ASIC-generated clock and generate a synchronized count in response to a reset signal from the memory controller; and
a data circuit comprising;
a FIFO buffer arranged to receive a data input from the DDR memory device, the strobe signals, and the strobe count signal, the HFO buffer generating a read data signal; and
a second synchronizer arranged to receive the read data signal, the ASIC-generated clock, and the synchronized count, the second synchronizer generating a representation of the read data signal in synchronization with the ASIC-generated clock.
8 Assignments
0 Petitions
Accused Products
Abstract
An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock.
-
Citations
24 Claims
-
1. An input/output interface for communicating between an application specific integrated circuit (ASIC) with a memory controller and a double data rate (DDR) memory device, the interface comprising:
-
a strobe circuit comprising; a preamble logic element arranged to receive strobe signals from the DDR memory device and generate a preamble signal; a first counter arranged to receive the preamble signal and the strobe signals, the first counter generating a strobe count signal; a second counter arranged to receive a read enable signal and an ASIC-generated clock, the second counter generating a read count signal; a strobe park circuit arranged to receive the preamble signal, the read count signal and the strobe count signal, the strobe park circuit generating a control signal that controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when the ASIC is not receiving data from the DDR memory device; and a first synchronizer arranged to receive the ASIC-generated clock and generate a synchronized count in response to a reset signal from the memory controller; and a data circuit comprising; a FIFO buffer arranged to receive a data input from the DDR memory device, the strobe signals, and the strobe count signal, the HFO buffer generating a read data signal; and a second synchronizer arranged to receive the read data signal, the ASIC-generated clock, and the synchronized count, the second synchronizer generating a representation of the read data signal in synchronization with the ASIC-generated clock. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. A method for communicating between an application specific integrated circuit (ASIC) and a double data rate (DDR) memory device, the method comprising:
-
in a read mode; detecting a strobe preamble; using a state machine to activate strobe receiver output signals in response to the strobe preamble; receiving an indication via signal transitions in an ASIC-generated clock and a read data enable signal of a data string length to be read from the DDR memory device; generating a first count of ASIC-generated clock signal transitions while receiving data from the DDR memory device; generating a second count of incoming strobe signal transitions while receiving data from the DDR memory device; determining when the read data enable signal transitions; generating a control signal when the first count and the second count are equal; and using the state machine to deactivate the strobe receiver output signals in response to the combination of the read data control signal transition and the control signal; in a write mode; generating a source clock signal responsive to the ASIC-generated clock; generating a synchronizing signal as a function of the source clock signal and a select one of three stages from a domain crossing circuit; generating a write-leveled representation of the source clock signal and the synchronizing signal; generating a third count responsive to transitions of the source clock signal and the synchronizing signal; generating a fourth count responsive to transitions of the write-leveled representation of the source clock signal and the write-leveled representation of the synchronizing signal; controllably latching data to be written to the DDR memory device to a first latch and a second latch in accordance with the third count; and controllably switching between an output of the first latch and an output of the second latch in accordance with the fourth count to generate a data output signal. - View Dependent Claims (17, 18, 19, 20, 21)
-
-
22. An input/output interface for communicating with a double data rate (DDR) memory device, the interface comprising:
a state machine implemented in a strobe park circuit, the state machine operating in multiple clock domains in accordance with both synchronous and asynchronous inputs, the state machine comprising four states responsive to the synchronous and asynchronous inputs, a first state defining a strobe park condition and each of a second state, a third state and a fourth state defining an active strobe condition. - View Dependent Claims (23, 24)
Specification