PROTECTION LAYER FOR ADHESIVE MATERIAL AT WAFER EDGE

• US 20110065238A1
• Filed: 04/29/2010
• Published: 03/17/2011
• Est. Priority Date: 09/14/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: SHUE, Shau-Lin, WU, Weng-Jin, CHIOU, Wen-Chih
• Granted Patent: US 8,252,665 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A wafer is attached to a carrier by using an adhesive layer, and a portion of the adhesive layer is exposed adjacent to an edge of the wafer. After thinning the wafer, a protection layer is provided to cover the exposed portion of the adhesive layer. A plurality of dies is bonded onto the thinned wafer, and then the thinned wafer and the dies are encapsulated with a molding compound.

Claims

1. A method, comprising:

providing a wafer having a first surface and a second surface opposite to the first surface;

attaching the first surface of the wafer to a carrier by using an adhesive layer, exposing a portion of the adhesive layer adjacent to an edge of the wafer;

thinning the wafer from the second surface, forming a thinned wafer;

forming a protection layer to cover the exposed portion of the adhesive layer;

bonding a plurality of dies onto the thinned wafer; and

encapsulating the thinned wafer and the plurality of dies with a molding compound.

2. The method of claim 1, wherein the protection layer covers the edge of the wafer.

3. The method of claim 1, wherein the protection layer covers a portion of the carrier adjacent to the edge of the wafer.

4. The method of claim 1, wherein the protection layer covers at least a portion of the second surface of the wafer.

5. The method of claim 1, wherein the protection layer comprises at least one of an oxide film, a nitride film, a carbide film, a dry film, a spin-on material film and combinations thereof.

6. The method of claim 1, wherein the wafer comprises:

a semiconductor substrate having a front surface and a back surface;

a through via filled with a conductive material passing through at least a part of the semiconductor substrate; and

integrated circuits formed on the front surface of the semiconductor substrate.

7. The method of claim 6, wherein after thinning the wafer, one end of the through via is exposed on the back surface of the semiconductor substrate.

8. The method of claim 6, wherein the protection layer is formed on the back surface of the semiconductor substrate after thinning the wafer.

9. The method of claim 7, further comprising forming a conductive structure on the exposed end of the through via before bonding the plurality of dies onto the thinned wafer.

10. The method of claim 9, wherein the conductive structure comprises at least one of solder, copper, and a combination thereof.

11. The method of claim 9, wherein the conductive structure comprises a redistribution layer (RDL).

12. A method, comprising:

providing a wafer having a first surface and a second surface opposite to the first surface;

attaching the first surface of the wafer to a carrier by using an adhesive layer, exposing a portion of the adhesive layer adjacent to an edge of the wafer;

thinning the wafer from the second surface, forming a thinned wafer;

forming a protection layer to cover the exposed portion of the adhesive layer, and the edge of the wafer;

bonding a die onto the thinned wafer;

encapsulating the thinned wafer and the die with a molding compound; and

removing the carrier.

13. The method of claim 12, wherein the protection layer covers a portion of the carrier adjacent to the edge of the wafer.

14. The method of claim 12, wherein the protection layer comprises at least one of an oxide film, a nitride film, a carbide film, a dry film, a spin-on material film or combinations thereof.

15. The method of claim 12, wherein the wafer comprises:

a semiconductor substrate having a front surface and a back surface;

a through via filled with a conductive material passing through at least a part of the semiconductor substrate; and

integrated circuits formed on the front surface of the semiconductor substrate.

16. The method of claim 15, wherein after thinning the wafer, one end of the through via is exposed on the back surface of the semiconductor substrate.

17. The method of claim 15, wherein the protection layer is formed on the back surface of the semiconductor substrate after thinning the wafer.

18. The method of claim 17, further comprising forming a conductive structure on the exposed end of the through via before bonding a plurality of the dies onto the thinned wafer.

19. The method of claim 18, wherein the conductive structure comprises at least one of solder, copper or a combination thereof.

20. The method of claim 18, wherein the conductive structure comprises a redistribution layer (RDL).