Method And Apparatus For Controlling A Harmonic Rejection Mixer

• US 20110065411A1
• Filed: 11/16/2010
• Published: 03/17/2011
• Est. Priority Date: 06/29/2007
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Alessandro Piovaccari, Aslamali A. Rafi
• Inventors: Rafi, Aslamali A., Piovaccari, Alessandro
• Granted Patent: US 8,543,077 B2
• Time in Patent Office: Days
• US Class Current: 455/323
• CPC Class Codes: H03D 2200/0025 Gain control circuits
• CPC Class Codes: H03D 2200/0084 Lowering the supply voltage and saving power
• CPC Class Codes: H03D 2200/0086 Reduction or prevention of harmonic frequencies
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1458 Double balanced arrangements, i.e. where both input signals are differential
• CPC Class Codes: H03D 7/1483 comprising components for selecting a particular frequency component of the output
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04N 5/455 Demodulation-circuits

Abstract

In one embodiment, the present invention includes a method for receiving a radio frequency (RF) signal and mixing the RF signal with a master clock to obtain a mixed signal, cyclically rotating the mixed signal to each of N gain stages for at least one cycle of the master clock, and summing the outputs of the N gain stages to provide an output signal.

Claims

1. A method comprising:

receiving an incoming radio frequency (RF) signal and mixing the incoming RF signal with a master clock, the master clock corresponding to a multiplied version of a local oscillator (LO) frequency, to obtain a mixed signal;

cyclically rotating the mixed signal to each of a plurality of N gain stages for at least one cycle of the master clock during a cycle of the LO; and

summing the outputs of the plurality of N gain stages to provide an output signal.

2. The method of claim 1, further comprising cyclically rotating the mixed signal from a first one to a second one of the plurality of N gain stages when the master clock is at a low value.

3. The method of claim 1, wherein the plurality of N gain stages each comprises an impedance corresponding to a weighted value obtained from a unitary impedance value and a predetermined weighted value.

4. The method of claim 3, wherein the plurality of N gain stages further comprises a unity gain buffer having an output coupled to the impedance.

5. The method of claim 1, further comprising cyclically rotating the mixed signal such that each of the plurality of N gain stages is to receive the mixed signal for a predetermined portion of the LO cycle.

6. The method of claim 5, further comprising cyclically rotating the mixed signal to less than all of the plurality of N gain stages, based at least in part on a frequency of the incoming RF signal.

7. The method of claim 6, further comprising reducing or preventing harmonic rejection by matching passive components in the plurality of N gain stages, wherein an RF mixer that mixes the incoming RF signal includes a single differential transconductor.

8. The method of claim 1, further comprising cyclically rotating positive and negative portions of the mixed signal in a complementary fashion to each of first and second sets of the plurality of N gain stages.

9. The method of claim 8, wherein each of the plurality of N gain stages includes a gain buffer having an output coupled to an impedance having a first weighted value or a second weighted value.

10. The method of claim 9, wherein the first weighted value corresponds to a ratio of a unitary impedance value and a predetermined value, wherein the predetermined value equals

11. A method comprising:

receiving a request for a channel at a first frequency;

determining a number of stages N to be enabled in a mixer based at least in part on the first frequency;

selecting a master clock frequency corresponding to a multiplied version of a local oscillator (LO) frequency, wherein the multiplied version corresponds to N×

LO and providing the master clock frequency to a mixer; and

mixing an incoming radio frequency (RF) signal that includes the channel with the master clock frequency and providing a mixed signal to each of N stages individually for a portion of each LO cycle.

12. The method of claim 11, further comprising summing an output of each of the N stages for each LO cycle.

13. The method of claim 11, further comprising determining N to be less than all available stages if the channel is in a band less than a predetermined frequency.

14. The method of claim 11, further comprising receiving a request for the channel at the first frequency.

15. The method of claim 14, further comprising:

receiving a second request for a second channel at a second frequency; and

dynamically updating a number of stages N to be enabled based on the second frequency.

16. The method of claim 15, further comprising determining the number of stages N based at least in part on a power consumption level for a receiver.

17. The method of claim 16, further comprising determining the number of stages N based at least in part on a harmonic rejection level for the receiver.

18. An apparatus comprising:

a low noise amplifier (LNA) to receive an incoming radio frequency (RF) signal;

a mixer to mix the incoming RF signal with a master clock to obtain a mixed signal, the master clock corresponding to a multiplied version of a local oscillator (LO) frequency;

a plurality of N gain stages each to receive a cyclical rotation of the mixed signal for at least one cycle of the master clock during a cycle of the LO; and

a summer to sum the outputs of the plurality of N gain stages to provide an output signal.

19. The apparatus of claim 18, further comprising a switch to cyclically rotate the mixed signal from a first one to a second one of the plurality of N gain stages when the master clock is at a low value.

20. The apparatus of claim 18, wherein the plurality of N gain stages each comprises an impedance corresponding to a weighted value obtained from a unitary impedance value and a predetermined weighted value.