MAIN MEMORY WITH NON-VOLATILE MEMORY AND DRAM

• US 20110066790A1
• Filed: 09/17/2009
• Published: 03/17/2011
• Est. Priority Date: 09/17/2009
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Shah, Mehul A., Faraboschi, Paolo, Oliveira Dias, Eduardo Argollo de JR., Mogul, Jeffrey Clifford
• Granted Patent: US 8,296,496 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

One embodiment is main memory that includes a combination of non-volatile memory (NVM) and dynamic random access memory (DRAM). An operating system migrates data between the NVM and the DRAM.

Claims

1. An electronic device, comprising:

main memory that includes a combination of non-volatile memory (NVM) and dynamic random access memory (DRAM); and

an operating system that allocates and migrates data between the NVM and the DRAM.

2. The electronic device of claim 1, wherein the NVM is flash memory.

3. The electronic device of claim 1, wherein the operating system buffers pages in a DRAM buffer while the pages are being migrated from the DRAM to the NVM to account for a slower write speed to the NVM.

4. The electronic device of claim 1, wherein the NVM and the DRAM are included on a dual in-line memory module (DIMM).

5. The electronic device of claim 1, wherein the operating system uses a policy that determines a time-to-next-write (TTNW) for pages stored in the DRAM to determine whether to migrate the pages from the DRAM to the NVM.

6. The electronic device of claim 1, wherein the operating system uses a policy that accounts for wear-out of the NVM to determine whether to migrate pages from the DRAM to the NVM.

7. The electronic device of claim 1, wherein the NVM is phase-change random access memory (PC-RAM).

8. A dual in-line memory module (DIMM), comprising:

a dynamic random access memory (DRAM); and

a flash memory coupled to the DRAM, wherein migration of data between the DRAM and the flash memory is controlled by an operating system.

9. The DIMM of claim 8, wherein the flash memory includes NAND flash or NOR flash.

10. The DIMM of claim 8, wherein data migrating between the DRAM and the flash memory is buffered to avoid delays caused by slower read or write speeds of the flash memory.

11. The DIMM of claim 8 further comprising, an application specific integrated circuit (ASIC) that copies data from a buffer to the DRAM during migration of the data from the flash memory to the DRAM.

12. The DIMM of claim 8 further comprising, a buffer that temporarily stores pages during migration of the pages to the flash memory.

13. The DIMM of claim 8, wherein the DIMM stores copy and erase commands for migrating data between the flash memory and the DRAM.

14. The DIMM of claim 8, wherein the operating system tracks an erase-count for the flash memory to determine where to migrate pages in the flash memory.

15. A method implemented by a computer, comprising:

controlling, by an operating system, both where to allocate data and when to migrate the data from non-volatile memory (NVM) on a dual in-line memory module (DIMM) to dynamic random access memory (DRAM) on the DIMM.

16. The method of claim 15 further comprising, using, by the operating system, a set of heuristics to determine when to migrate the data to the NVM, wherein the set of heuristics includes statistics about time between writes (TBW) for the data being migrated.

17. The method of claim 15 further comprising, using, by the operating system, a set of heuristics to determine when to migrate the data to the NVM, wherein the set of heuristics includes a type of page being migrated to the DRAM and a type of file to which the page is being mapped.

18. The method of claim 15 further comprising, moving a page back from the DRAM to the NVM when the operating system predicts the page will be written.

19. The method of claim 15 further comprising, collecting, by the operating system, data on how frequently a page is written to determine a time to next write for the page.

20. The method of claim 15 further comprising, minimizing occurrence of block erase operations in the NVM to decrease a wear-out of the NVM.