Memory Array Power Cycling

• US 20110066869A1
• Filed: 09/16/2009
• Published: 03/17/2011
• Est. Priority Date: 09/16/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Fai, Anthony, Byom, Matthew, Wakrat, Nir Jacob
• Granted Patent: US 8,489,907 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.

Claims

1. A method performed by a non-volatile memory device coupled to a host system in a non-volatile memory system, where the host system independently powers a controller and a memory array in the non-volatile memory device with physically separate power rails, the method comprising:

receiving a power cycle request signal from the non-volatile memory device; and

decoding the power cycle request signal; and

power cycling the controller or the memory array based on the decoded power cycle request signal.

2. The method of claim 1, where power cycling includes turning off the power or reducing the power to a first power rail coupled to the controller, or turning off the power or reducing the power to a second power rail coupled to the memory array.

3. The method of claim 1, where the non-volatile memory device is a managed NAND device.

4. The method of claim 1, where the power cycle request signal is based on a power state.

11. The method of claim 1, where power cycling includes turning off the power or reducing the power to a first power rail coupled to the controller, or turning off the power or reducing the power to a second power rail coupled to the memory array.

12. The method of claim 1, where the non-volatile memory device is a managed NAND device.

13. The method of claim 1, where the power cycle request is based on a power state.

5. A non-volatile memory system, comprising:

a host system;

a non-volatile memory device coupled to the host system;

a memory array included in the non-volatile memory device and coupled to a power source in the host system by a first power rail; and

a controller included in the non-volatile memory device and coupled to the power source, or a different power source of the host system, by a second power rail, the controller configurable for sending a power cycle request signal to the host system.

6. The system of claim 5, where the host system receives and decodes the power cycle request signal, and performs a power cycle on the first power rail or the second power rail based on the decoded power cycle request signal.

7. The system of claim 5, where the non-volatile memory device is a managed NAND device.

8. The system of claim 5, where the power cycle request signal is based on a power state of the non-volatile memory system.

9. The system of claim 5, where the non-volatile memory device includes a number of memory arrays, at least two of which can be power cycled through the first power rail.

10. A method performed by a host system in a non-volatile memory system, where the host system independently powers a controller and a memory array in the non-volatile memory device with physically separate power rails, the method comprising:

reading a status register in the controller to determine if a power cycle request signal is requested from the non-volatile memory device; and

decoding contents of the status register; and

power cycling the controller or the memory array based on the status register contents.

14. A non-volatile memory system, comprising:

a host system;

a non-volatile memory device coupled to the host system;

a memory array included in the non-volatile memory device and coupled to a power source in the host system by a first power rail; and

a controller included in the non-volatile memory device and coupled to the power source, or a different power source of the host system, by a second power rail,

where the controller is configurable for updating contents of a status register in the controller, and the host system is configurable for reading the status register and performing a power cycle on the first power rail or the second power rail based on the contents of the status register.

15. The system of claim 14, where the non-volatile memory device is a managed NAND device.

16. The system of claim 14, where the power cycle request is based on a power state of the non-volatile memory system.

17. The system of claim 14, where the non-volatile memory device includes a number of memory arrays, at least two of which can be power cycled through the first power rail.