PLUGGABLE TRANSCEIVER MODULE WITH ENHANCED CIRCUITRY

• US 20110066909A1
• Filed: 10/30/2009
• Published: 03/17/2011
• Est. Priority Date: 09/15/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Inventors: Skirmont, David Aaron, Kilkenny, Daniel Kiernan, Varanasi, Surya Prakash, Ko, Kung-Ling
• Granted Patent: US 8,161,332 B2
• Time in Patent Office: Days
• US Class Current: 714/746
• CPC Class Codes: H04B 10/40 Transceivers
• CPC Class Codes: H04L 1/004 by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00
• CPC Class Codes: H04L 1/203 Details of error rate determination, e.g. BER, FER or WER
• CPC Class Codes: H04L 2209/30 Compression, e.g. Merkle-Damgard construction
• CPC Class Codes: H04L 2209/34 Encoding or coding, e.g. Huffman coding or error correction
• CPC Class Codes: H04L 9/065 Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3

Abstract

Pluggable transceiver modules with additional functions and circuitry contained within the module. In a first embodiment, additional circuitry is added to determine bit error rates at the point of the module itself. This allows a much better diagnostic evaluation of location of problem. In an alternate embodiment, various logic is placed in the module. In a first alternate embodiment encryption/decryption units are placed in the converter module so that encryption and decryption operations on the serial bitstream do not need to be performed in a switch. Existing switches can be used but the interconnecting links can still be encrypted. A second alternate embodiment includes compression/decompression units placed in the module to allow effective higher throughput on the selected links.

Claims

1. A pluggable transceiver comprising:

a receive section including;

receive digital function circuitry configured to monitor bit error rates of a serial signal; and

a transmit section including;

transmit digital function circuitry configured to monitor bit error rates of a serial signal.

2. The pluggable transceiver of claim 1, further comprising:

a controller having a control communication interface and connected to the receive section and transmit section,

wherein said receive section further includes;

a receive amplifier having an input coupled to a received signal and having an output digital signal coupled to said receive digital function circuitry; and

a balanced output driver having an input coupled to said receive digital function circuitry and having an output which provides a balanced digital output signal,

wherein said transmit section further includes;

a balanced input buffer having an input to receive a balanced digital signal and having an output digital signal coupled to said transmit digital function circuitry; and

a transmit amplifier having an input coupled to the transmit digital function circuitry and having an output signal coupled to a transceiver output signal, and

wherein said controller controls said receive and transmit amplifiers and said receive and transmit digital function circuitry.

3. The pluggable transceiver of claim 2,

wherein said receive section further includes:

a forward error correction decoder having an input coupled to the receive amplifier output and having an output connected to said receive digital function circuitry, and

a forward error detection encoder having an input connected to said receive digital function circuitry and having an output coupled to the balanced output driver input; and

wherein said transmit section further includes;

a forward error correction decoder having an input coupled to the balanced input buffer output and having an output connected to said transmit digital function circuitry; and

a forward error detection encoder having an input connected to said transmit digital function circuitry and having an output coupled to the transmit amplifier input.

4. The pluggable transceiver of claim 3,

wherein said receive digital function circuitry further includes:

a line decoder circuit having an input connected to said receive amplifier output and having an output connected to the forward error detection decoder input; and

a line encoder circuit having an input connected to the forward error detection encoder output and having an output connected to the balanced output driver input; and

wherein the transmit digital function circuitry further includes;

a line decoder circuit having an input connected to the balanced input buffer output and having an output connected to the forward error detection decoder input; and

a line encoder circuit having an input connected to the forward error detection encoder output and having an output connected to the transmit amplifier input.

5. The pluggable transceiver of claim 2,

wherein said receive digital function circuitry further includes:

a photo-detector which provides an output electrical signal based on a received optical signal to the input of said receive amplifier; and

wherein the transmit digital function circuitry further includes;

a laser diode connected to said transmit amplifier output signal and providing an optical output signal.

6. A pluggable transceiver comprising:

a receive section including;

receive digital function circuitry configured to decrypt a serial signal; and

a transmit section including;

transmit digital function circuitry configured to encrypt a serial signal.

7. The pluggable transceiver of claim 6, wherein said receive digital function circuitry is further configured to decompress the serial signal, and wherein said transmit digital function circuitry is further configured to compress the serial signal.

8. The pluggable transceiver of claim 7, wherein said receive digital function circuitry is further configured to configured to monitor bit error rates of a serial signal, and wherein said transmit digital function circuitry is further configured to configured to monitor bit error rates of a serial signal.

9. The pluggable transceiver of claim 6, further comprising:

a controller having a control communication interface and connected to the receive section and transmit section,

wherein said receive section further includes;

a receive amplifier having an input coupled to a received signal and having an output digital signal coupled to said receive digital function circuitry; and

a balanced output driver having an input coupled to said receive digital function circuitry and having an output which provides a balanced digital output signal,

wherein said transmit section further includes;

a balanced input buffer having an input to receive a balanced digital signal and having an output digital signal coupled to said transmit digital function circuitry; and

a transmit amplifier having an input coupled to the transmit digital function circuitry and having an output signal coupled to a transceiver output signal, and

wherein said controller controls said receive and transmit amplifiers and said receive and transmit digital function circuitry.

10. The pluggable transceiver of claim 9,

wherein said receive digital function circuitry further includes:

a line decoder circuit having an input connected to said receive amplifier output and having an output connected to said receive digital function circuitry; and

a line encoder circuit having an input connected to the said receive digital function circuitry and having an output connected to the balanced output driver input; and

wherein the transmit digital function circuitry further includes;

a line decoder circuit having an input connected to the balanced input buffer output and having an output connected to said transmit digital function circuitry; and

a line encoder circuit having an input connected to said transmit digital function circuitry and having an output connected to the transmit amplifier input.

11. The pluggable transceiver of claim 9,

wherein said receive digital function circuitry further includes:

a photo-detector which provides an output electrical signal based on a received optical signal to the input of said receive amplifier; and

wherein the transmit digital function circuitry further includes;

a laser diode connected to said transmit amplifier output signal and providing an optical output signal.

12. A pluggable transceiver comprising:

a receive section including;

receive digital function circuitry configured to decompress a serial signal; and

a transmit section including;

transmit digital function circuitry configured to compress a serial signal.

13. The pluggable transceiver of claim 12, further comprising:

a controller having a control communication interface and connected to the receive section and transmit section,

wherein said receive section further includes;

a receive amplifier having an input coupled to a received signal and having an output digital signal coupled to said receive digital function circuitry; and

a balanced output driver having an input coupled to said receive digital function circuitry and having an output which provides a balanced digital output signal,

wherein said transmit section further includes;

a balanced input buffer having an input to receive a balanced digital signal and having an output digital signal coupled to said transmit digital function circuitry; and

a transmit amplifier having an input coupled to the transmit digital function circuitry and having an output signal coupled to a transceiver output signal, and

wherein said controller controls said receive and transmit amplifiers and said receive and transmit digital function circuitry.

14. The pluggable transceiver of claim 13,

wherein said receive digital function circuitry further includes:

a line decoder circuit having an input connected to said receive amplifier output and having an output connected to said receive digital function circuitry; and

a line encoder circuit having an input connected to said receive digital function circuitry and having an output connected to the balanced output driver input; and

wherein the transmit digital function circuitry further includes;

a line decoder circuit having an input connected to the balanced input buffer output and having an output connected to said transmit digital function circuitry; and

a line encoder circuit having an input connected to said transmit digital function circuitry and having an output connected to the transmit amplifier input.

15. The pluggable transceiver of claim 13,

wherein said receive digital function circuitry further includes:

a photo-detector which provides an output electrical signal based on a received optical signal to the input of said receive amplifier; and

wherein the transmit digital function circuitry further includes;

a laser diode connected to said transmit amplifier output signal and providing an optical output signal.

16. A network device comprising:

a pluggable transceiver that monitors bit error rates;

a processor coupled to said pluggable transceiver; and

software, running on said processor, that causes said processor to obtain bit error rate values from said pluggable transceiver and to provide said bit error rate values for use by a user.

17. A network device comprising:

a pluggable transceiver that encrypts and decrypts serial signals;

a processor coupled to said pluggable transceiver; and

software, running on said processor, that causes said processor to provide a key to said pluggable transceiver and to activate encryption and decryption by said pluggable transceiver.

18. The network device of claim 17, wherein said pluggable transceiver further compresses and decompresses serial signals, and

wherein said software further causes said processor to activate compression and decompression by said pluggable transceiver.

19. The network device of claim 18, wherein said pluggable transceiver further monitors bit error rates, and

Wherein said software further causes said processor to obtain bit error rate values from said pluggable transceiver and to provide said bit error rate values for use by a user.

20. A network device comprising:

a pluggable transceiver that compresses and decompresses serial signals;

a processor coupled to said pluggable transceiver; and

software, running on said processor, that causes said processor to activate compression and decompression by said pluggable transceiver.

21. A method comprising:

detecting bit error rates in a serial signal in a pluggable transceiver;

reading said detected bit error rates from the pluggable transceiver; and

providing said read, detected bit error rates for use by a user.

22. A method comprising:

providing a key to a pluggable transceiver; and

encrypting and decrypting serial signals in the pluggable transceiver.

23. The method of claim 22, further comprising:

compressing and decompressing the serial signals in the pluggable transceiver; and

activating the compression and decompression in the pluggable transceiver.

24. The method of claim 23, further comprising:

detecting bit error rates in a serial signal in the pluggable transceiver;

reading said detected bit error rates from the pluggable transceiver; and

providing said read, detected bit error rates for use by a user.

25. A method comprising:

selectively compressing and decompressing serial signals in a pluggable transceiver; and

activating the compression and decompression in the pluggable transceiver.