AUTONOMOUS MEMORY ARCHITECTURE

• US 20110067039A1
• Filed: 09/11/2009
• Published: 03/17/2011
• Est. Priority Date: 09/11/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hulbert, Jared, Leinwander, Mark, Eilert, Sean
• Granted Patent: US 9,779,057 B2
• Time in Patent Office: Days
• US Class Current: 719/328
• CPC Class Codes: G06F 15/17318 Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all

Abstract

An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass configuration routing information and initiate instructions to disperse portions of the database to neighboring die using an interface that handles inter-die communication. Information is then extracted from the pool of autonomous memory and passed through a host interface to the host controller.

Claims

1. A method for a host to operate with a distributed memory sub-system, comprising:

transferring a database from the host to the memory sub-system along with information about how the database is organized;

using hardware primitives in an autonomous memory of the memory sub-system to manipulate memory contents;

downloading algorithms from the host to the memory sub-system for processing information in the database; and

broadcasting high level commands by the host to the memory sub-system rather than providing specific commands and addresses to the autonomous memory to perform a high level function.

2. The method of claim 1 where the autonomous memory is using its own operating system.

3. The method of claim 1 where the host is assigning a unique static address to the autonomous memory as determined by a route to the autonomous memory.

4. The method of claim 1 where the host is dynamically determining an address of the autonomous memory device while the memory sub-system operates.

5. The method of claim 1 where the autonomous memory is building a routing table using a scan technique to keep track of other devices within the memory sub-system.

6. The method of claim 5 where the autonomous memory is storing a latency cost based on location of the autonomous memory in communication with another autonomous memory.

7. The method of claim 1 where a search and destroy algorithm is executing simultaneously on each autonomous memory in the memory sub-system to isolate and disable any occurrence of a target virus.

8. A method of operating a memory sub-system;

comprising;

transferring a database from a host to the memory sub-system along with information about how the database is organized;

broadcasting a high level command to the memory sub-system; and

executing the high level command simultaneously in first and second autonomous memory located within the memory sub-system with results determined in a time that is independent of a number of devices operating in the memory sub-system.

9. The method of operating the memory sub-system of claim 8 wherein the first autonomous memory interacts using a first interface for communicating with the host and a second interface for communicating with the second autonomous memory in the memory sub-system.

10. The method of operating a memory sub-system of claim 8 wherein the second interface for communicating with the second autonomous memory includes a flexible interface on top of which a software Application Programming Interface (API) is built.

11. The method of operating a memory sub-system of claim 8 wherein the second interface for communicating with the second autonomous memory in the memory sub-system includes passing messages that contain a command and a list of parameters.

12. The method of operating a memory sub-system of claim 11 wherein passing messages further includes passing data, addressing information that refers to data in an array of the second autonomous memory, and object identifiers that reference an object located in the array.

13. A method of operating an autonomous memory in a distributed memory sub-system;

comprising;

storing a database downloaded from a host through a host interface;

dynamically determining a configuration of multiple die in the distributed memory sub-system;

parsing and sending out operations to the multiple die in the distributed memory sub-system to be executed autonomously; and

accumulating results and reporting to the host when the operation is complete.

14. The method of operating an autonomous memory of claim 13 further including:

executing stored routines provided by libraries to support building applications.

15. The method of operating an autonomous memory of claim 13 further including:

using acceleration hardware for computations and manipulations of the contents stored within the autonomous memory.

16. The method of operating an autonomous memory of claim 13 further including:

tracking locations of database tables among the multiple die in the distributed memory sub-system to independently process data in the stored database to return the results to the host.

17. A method of connecting an autonomous memory device in a distributed memory sub-system;

comprising;

receiving a database at a host interface that is downloaded from a host controller; and

initiating instructions that are dispersed to neighboring die using an interface to handle inter-die communication ports within a pool of autonomous memory.

18. The method of claim 17 further including:

extracting information from the pool of autonomous memory that is passed through the host interface to the host controller.

19. The method of claim 17 further including:

receiving software downloaded from the host controller that allow the autonomous memory device to control other memory devices that communicate within the pool of autonomous memory.

20. The method of claim 17 further including:

passing routing information within the pool of autonomous memory.