Trench MOSFET with high cell density

• US 20110068389A1
• Filed: 09/21/2009
• Published: 03/24/2011
• Est. Priority Date: 09/21/2009
• Status: Abandoned Application

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hsieh, Fu-Yuan
• Application Number:
  US12/585,639
• Publication Number:
  US 20110068389A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOSFET with high cell density is disclosed where there is a heavily doped contact region on the top surface of mesas between a pair of gate trenches. The present invention can prevent the degradation of avalanche capability when shrinking the device in prior art.

Claims

1. A trench MOSFET comprising:

a plurality of gate trenches formed in epitaxial layer of a first conductivity doping type and filled with gate conductive layer over gate insulation layer;

said plurality of gate trenches defining a plurality of mesas, each of said mesas being between every two adjacent said gate trenches;

a plurality of source regions of a first conductivity doping type formed inside said mesas, each of said source regions having a side portion exposed at a sidewall of each of said gate trenches;

a first body region of a second conductivity doping type formed between a pair of said gate trenches;

a second body region of said second conductivity doping type having heavier doping concentration than said first body region, formed inside said mesas and between a pair of said source regions;

a heavily-doped contact region of said second conductivity doping type on top of each mesa over said source region and said second body region, said heavily-doped contact region having a heavier doping concentration than said second body region; and

a front metal over top surface of said mesas and extending into each gate trench, wherein said front metal is isolated from said gate conductive area inside said gate trenches.

2. The MOSFET of claim 1, wherein said gate conductive layer is doped poly.

3. The MOSFET of claim 1, wherein said gate insulation layer is composed of oxide.

4. The MOSFET of claim 1, wherein said gate insulation layer at the bottom of each gate trench is thicker than or equal to that along the sidewalls of each gate trench.

5. The MOSFET of claim 1, wherein there is a doped region of said first conductivity doping type around the bottom of each gate trench, said doped region has a heavier doping concentration than said epitaxial layer.

6. The MOSFET of claim 1, wherein said front metal is isolated from said gate conductive area by a PSG layer.

7. The MOSFET of claim 1, wherein there is a barrier layer Ti/TiN or Co/TiN or Ta/TiN between the front metal and the top surface of said mesas, also between the front metal and the sidewalls of each gate trench.

8. A trench MOSFET comprising:

a plurality of gate trenches formed in epitaxial layer of a first conductivity doping type and filled with gate conductive layer over gate insulation layer;

said plurality of gate trenches defining a plurality of mesas, each of said mesas being between every two adjacent said gate trenches;

a plurality of source regions of a first conductivity doping type formed inside said mesas, each of said source regions having a side portion exposed at a sidewall of each of said gate trenches;

a first body region of a second conductivity doping type formed between a pair of said gate trenches;

a second body region of said second conductivity doping type having heavier doping concentration than said first body region, formed inside said mesas and between a pair of said source regions;

a heavily-doped contact region of said second conductivity doping type on top of each mesa over said source region and said second body region, said heavily-doped contact region having a heavier doping concentration than said second body region; and

a plurality of metal plugs filled into the upper portion of said gate trenches, wherein said plurality of metal plugs is isolated from said gate conductive layer inside said gate trenches; and

a front metal over top surface of said mesas and said plurality of metal plugs.

9. The MOSFET of claim 8, wherein said gate conductive layer is doped poly.

10. The MOSFET of claim 8, wherein said gate insulation layer is composed of oxide.

11. The MOSFET of claim 8, wherein said gate insulation layer at the bottom of each gate trench is thicker than or equal to that along the sidewalls of each gate trench.

12. The MOSFET of claim 8, wherein there is a doped region of said first conductivity doping type around the bottom of each gate trench, said doped region has a heavier doping concentration than said epitaxial layer.

13. The MOSFET of claim 8, wherein said metal plug is isolated from said gate conductive area by a PSG layer.

14. The MOSFET of claim 8, wherein said metal plug is W metal plug.

15. The MOSFET of claim 8, wherein there is a barrier layer Ti/TiN or Co/TiN or Ta/TiN between each metal plug and the sidewalls of each gate trench.

16. The MOSFET of claim 8, wherein there is a resistance-reduction layer Ti or Ti/TiN between said front metal and the top surface of said mesa, also between the front metal and top surface of said metal plugs.

17. A Method for making a trench MOSFET comprising:

forming a plurality of gate trenches within epitaxial layer and filled with gate conductive layer padded by a gate insulation layer;

implanting with a first body dopant and diffusing said first body dopant to form said first body regions;

implanting with a second body dopant and diffusing said second body dopant to form said second body regions over said first body regions;

removing the upper portion of said gate conductive layer;

removing said gate insulation layer from the top surface of said second body region and from the upper sidewalls of gate trenches;

depositing a doped insulation layer on top of said gate conductive layer within said gate trenches to form source region;

etching said insulation layer to a thinner thickness; and

implanting with heavy contact dopant to form said heavily-doped contact region on top of each mesa.

18. The method of claim 17 further comprising:

depositing a barrier layer along the top surface of said heavily-doped contact region and the upper sidewalls of said gate trenches; and

depositing front metal onto said barrier layer and extending into said gate trenches.

19. The method of claim 17 further comprising:

depositing a barrier layer along the upper sidewalls of said gate trenches;

forming metal plugs to fill the upper portion of said gate trenches; and

depositing front metal covering the top surface of said heavily-doped contact region and said metal plugs.

20. The method of claim 19 further comprising depositing a resistance-reduction layer covering the top surface of said heavily-doped contact region and said metal plugs before the deposition of front metal.

21. The method of claim 17 further comprising forming a thicker gate insulation layer at gate trench bottom before the deposition of gate conductive layer.

22. The method of claim 17 further comprising forming a doped region of the same conductivity doping type as said epitaxial layer around the bottom of each gate trench before the formation of said gate insulation layer, said doped reigon having a heavier doping concentration than said epitaxial layer.