SUBSTRATE SYMMETRICAL SILICIDE SOURCE/DRAIN SURROUNDING GATE TRANSISTOR

• US 20110068418A1
• Filed: 09/23/2009
• Published: 03/24/2011
• Est. Priority Date: 09/23/2009
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: LUNG, HSIANG-LAN
• Granted Patent: US 8,164,146 B2
• Time in Patent Office: Days
• US Class Current: 257/413
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Field effect transistors described herein include first and second terminals vertically separated by a channel region. The first and second terminals comprise first and second silicide elements respectively. The first silicide element prevents the migration of carriers from the first terminal into the underlying semiconductor body or adjacent devices which can activate parasitic devices. The first silicide element is also capable of acting as a low resistance conductive line for interconnecting devices or elements. The second silicide element provides a low resistance contact between the second terminal and overlying elements.

Claims

1. A transistor comprising:

a first terminal comprising a first silicide element on a semiconductor body comprising silicon;

a second terminal overlying the first terminal and comprising a second silicide element;

a channel region separating the first and second terminals;

a gate terminal having an inside surface surrounding the channel region; and

a dielectric separating the channel region from the gate terminal.

2. The transistor of claim 1, wherein:

the first terminal further comprises a first doped region on the first silicide element, the first silicide element separating the first doped region from the semiconductor body; and

the second terminal further comprises a second doped region underlying the second silicide element.

3. The transistor of claim 1, wherein the channel region comprises intrinsically doped semiconductor material contacting the first and second silicide elements.

4. The transistor of claim 1, wherein the gate terminal is a metal material.

5. The transistor of claim 1, wherein the gate terminal comprises doped silicon material and a silicide conductor on the doped silicon material, the silicide conductor having a top surface co-planar with a top surface of the second silicide element.

6. The transistor of claim 5, further comprising a gate contact on the silicide conductor of the gate terminal.

7. The transistor of claim 1, wherein the channel region has a core comprising germanium, and a shell surrounding the core and comprising silicon.

8. The transistor of claim 1, wherein the channel region comprises single crystal silicon.

9. The transistor of claim 1, further comprising a source contact on the second silicide element of the second terminal.

10. The transistor of claim 1, further comprising a drain contact on the first silicide element of the first terminal.

11. A method for manufacturing a transistor, the method comprising:

providing a semiconductor body comprising silicon;

forming a first terminal on the semiconductor body, a second terminal overlying the first terminal, and a channel region separating the first and second terminals, wherein forming the first terminal comprises forming a first silicide element in the semiconductor body and separating the channel region from an underlying portion of the semiconductor body;

forming a gate terminal having an inside surface surrounding the channel region; and

forming a dielectric separating the channel region from the gate terminal.

12. The method of claim 11, wherein:

forming the first terminal further comprises forming a first doped region on the semiconductor body before forming the first silicide element, wherein forming the first silicide element separates the first doped region from the semiconductor body; and

forming the second terminal further comprises forming a second doped region on the channel region before forming the second silicide element, wherein forming the second silicide element comprises forming the second silicide element on the second doped region.

13. The method of claim 12, wherein forming the first and second terminals and the channel region comprise:

implanting dopants into the semiconductor body and forming dielectric trenches in the semiconductor body to define a strip of doped semiconductor body material, the strip comprising upper and lower portions having a first conductivity type and a middle portion having a second conductivity type different from the first conductivity type;

patterning the strip of doped semiconductor material to form a stack comprising the first and second doped regions and the channel region, the patterning exposing portions of the semiconductor body adjacent the stack;

depositing a silicide precursor on the exposed portions of the semiconductor body adjacent the stack;

forming the first silicide element by inducing reaction of the silicide precursor with the semiconductor body to consume silicon of the semiconductor body until the first silicide element separate the stack from an underlying portion of the semiconductor body.

14. The method of claim 13, including forming dielectric spacers on exposed sidewalls of the stack before said depositing the silicide precursor.

15. The method of claim 14, further comprising:

removing portions of the dielectric spacers to expose an outer surface of the channel region;

forming the dielectric on the exposed outer surface of the channel region;

forming the gate terminal surrounding the dielectric.

16. The method of claim 15, wherein forming the gate terminal and forming the second silicide element comprise:

depositing doped polysilicon material on the dielectric and overlying the stack;

planarizing the doped polysilicon material to expose a top surface of the second doped region of the stack; and

performing a silicide process to form the second silicide element on the second doped region and form a silicide conductor on the doped polysilicon material.

17. The method of claim 11, wherein the channel region comprises intrinsically doped semiconductor material contacting the first and second silicide elements.

18. The method of claim 11, wherein the gate terminal is a metal material.

19. The method of claim 11, wherein forming the channel region comprises growing the channel region on the semiconductor body using a nano-wire growth technique.

20. The method of claim 11, wherein the channel region has a core comprising germanium, and a shell surrounding the core and comprising silicon.