PACKAGE-ON-PACKAGE TYPE SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

• US 20110068481A1
• Filed: 08/31/2010
• Published: 03/24/2011
• Est. Priority Date: 09/23/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Tae-Sung, Kim, Kyung-Man, PARK, Sung-Kyu, Kim, Hye-Jin
• Granted Patent: US 8,399,992 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1082 : for improving alignment between containers, e.g. interlocking features
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Provided are a semiconductor package and a method for fabricating the same. The semiconductor package includes a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate and comprising a redistribution, and a molding layer molding the lower semiconductor chip, an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, with the upper package being stacked on the lower package. The semiconductor package further includes an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper and lower packages to each other, and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper and lower packages to each other.

Claims

1. A semiconductor package comprising:

a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate, a redistribution, and a molding layer molding the lower semiconductor chip;

an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, the upper package being stacked on the lower package;

an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper package and the lower package to each other; and

a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper package and the lower package to each other.

2. The semiconductor package of claim 1, wherein the electrical interconnector is disposed at a center portion of a bottom surface of the upper substrate, and the dummy interconnector is disposed adjacent to an edge portion of the upper substrate when compared to the electrical interconnector.

3. The semiconductor package of claim 2, wherein the dummy interconnector is disposed at an edge portion of the molding layer corresponding to an outer region of the semiconductor chip.

4. The semiconductor package of claim 1, wherein the dummy interconnector comprises at least one of a first dummy interconnector extending toward the lower semiconductor chip;

and a second dummy interconnector disposed further adjacent to an edge portion of the upper substrate when compared to the first dummy interconnector to extend toward the lower substrate in an outer region of the lower semiconductor chip.

5. The semiconductor package of claim 4, wherein the redistribution comprises:

a first redistribution connected to the electrical interconnector and electrically connected to the lower substrate; and

a second redistribution connected to the first dummy interconnector and not electrically connected to the lower substrate.

6. The semiconductor package of claim 5, wherein the molding layer comprises at least one of a mold via hole exposing the first redistribution to provide a disposition space for the electrical interconnector, a first dummy mold via hole exposing the second redistribution to provide a disposition space for the first dummy interconnector, and a second dummy mold via hole providing a disposition space of the second dummy interconnector,

wherein the first dummy mold via hole has an empty space which is not filled with the first dummy interconnector.

7. The semiconductor package of claim 4, wherein the upper substrate comprises a ball land connected to the electrical interconnector on a center portion thereof;

and

the upper substrate comprises a first dummy ball land connected to the first dummy interconnector, the first dummy ball land having a size less than a size of the ball land on the edge portion thereof.

8. The semiconductor package of claim 7, wherein the first dummy interconnector has a sectional area gradually increasing from an upper side connected to the first ball land to a lower side opposite to the upper side.

9. The semiconductor package of claim 8, wherein the upper substrate further comprises a second dummy ball land connected to the second dummy interconnector and having a size equal to or less than a size of the ball land on the edge thereof.

10. The semiconductor package of claim 9, wherein the second dummy interconnector has a same sectional area from an upper portion of the upper substrate toward a lower portion of the lower substrate or a sectional area gradually changing from the upper portion of the upper substrate toward the lower portion of the lower substrate.

11-20. -20. (canceled)