SEMICONDUCTOR DEVICE, POWER CIRCUIT, AND MANUFACTURING MKETHOD OF SEMICONDUCTOR DEVICE

• US 20110068852A1
• Filed: 09/22/2010
• Published: 03/24/2011
• Est. Priority Date: 09/24/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ito, Yoshiaki, Takahashi, Kei, Yamazaki, Shunpei
• Granted Patent: US 8,723,173 B2
• Time in Patent Office: Days
• US Class Current: 327/434
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The semiconductor device includes a first conductive layer over a substrate; an oxide semiconductor layer which covers the first conductive layer; a second conductive layer in a region which is not overlapped with the first conductive layer over the oxide semiconductor layer; an insulating layer which covers the oxide semiconductor layer and the second conductive layer; and a third conductive layer in a region including at least a region which is not overlapped with the first conductive layer or the second conductive layer over the insulating layer.

Claims

1. A semiconductor device comprising:

a first conductive layer over a substrate;

an oxide semiconductor layer over the first conductive layer;

a second conductive layer over the oxide semiconductor layer, wherein the second conductive layer is not overlapped with the first conductive layer;

an insulating layer over the oxide semiconductor layer and the second conductive layer; and

a third conductive layer over the insulating layer, wherein the third conductive layer comprises at least a first portion which is overlapped with neither the first conductive layer nor the second conductive layer.

2. The semiconductor device according to claim 1, wherein the third conductive layer is located between the first conductive layer and the second conductive layer.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer covers the first conductive layer.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is located so that part of the first conductive layer is not overlapped with the oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

6. The semiconductor device according to claim 1, wherein the third conductive layer comprises a second portion which is overlapped with the second conductive layer.

7. The semiconductor device according to claim 1,

wherein the first conductive layer serves as one of a source electrode and a drain electrode,

wherein the second conductive layer serves as the other of the source electrode and the drain electrode, and

wherein the third conductive layer serves as a gate electrode.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a crystal region at an upper superficial portion.

9. The semiconductor device according to claim 8, wherein the crystal region comprises In₂Ga₂ZnO₇ crystal.

10. The semiconductor device according to claim 1, wherein the second conductive layer is surrounded by the third conductive layer.

11. A power circuit comprising the semiconductor device according to claim 1, wherein the power circuit changes output voltage by switching an on state and off state of the semiconductor device in accordance with a pulse signal input to the third conductive layer.

12. A semiconductor device comprising:

an oxide semiconductor layer over a substrate;

a first conductive layer over the oxide semiconductor layer;

a second conductive layer over the oxide semiconductor layer, wherein the second conductive layer is located so as not overlapped with the first conductive layer;

an insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer; and

a third conductive layer over the insulating layer, wherein the third conductive layer comprises at least a first portion which is overlapped with neither the first conductive layer nor the second conductive layer.

13. The semiconductor device according to claim 12, wherein the third conductive layer is located between the first conductive layer and the second conductive layer.

14. The semiconductor device according to claim 12, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

15. The semiconductor device according to claim 12, wherein the third conductive layer comprises a second portion which is overlapped with the second conductive layer.

16. The semiconductor device according to claim 12,

wherein the first conductive layer serves as one of a source electrode and a drain electrode,

wherein the second conductive layer serves as the other of the source electrode and the drain electrode, and

wherein the third conductive layer serves as a gate electrode.

17. The semiconductor device according to claim 12, wherein the oxide semiconductor layer comprises a crystal region at an upper superficial portion.

18. The semiconductor device according to claim 17, wherein the crystal region comprises In₂Ga₂ZnO₇ crystal.

19. The semiconductor device according to claim 12, wherein the first conductive layer and the second conductive layer are located on the same surface.

20. The semiconductor device according to claim 12, wherein the second conductive layer is surrounded by the third conductive layer.

21. A power circuit comprising the semiconductor device according to claim 12, wherein the power circuit changes output voltage by switching an on state and off state of the semiconductor device in accordance with a pulse signal input to the third conductive layer.

22. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first conductive layer over a substrate;

forming an oxide semiconductor layer over the first conductive layer;

forming a second conductive layer over the oxide semiconductor layer so as not overlapped with the first conductive layer;

forming an insulating layer over the oxide semiconductor layer and the second conductive layer;

forming a third conductive layer over the insulating layer, wherein the third conductive layer is formed so as to comprise at least a first portion which is overlapped with neither the first conductive layer nor the second conductive layer.

23. The method for manufacturing a semiconductor device according to claim 22, wherein the third conductive layer is formed so as to be located between the first conductive layer and the second conductive layer.

24. The method for manufacturing a semiconductor device according to claim 22,

further comprising the step of forming a crystal region at an upper superficial portion of the oxide semiconductor layer by heating the oxide semiconductor layer,

wherein the second conductive layer is formed over the crystal region.

25. The method for manufacturing a semiconductor device according to claim 24, wherein the crystal region is formed by heating the oxide semiconductor layer at 500°

C. or higher.

26. The method for manufacturing a semiconductor device according to claim 22, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

27. The method for manufacturing a semiconductor device according to claim 22, wherein the third conductive layer is formed so as to comprise a second portion which is overlapped with the second conductive layer.

28. The method for manufacturing a semiconductor device according to claim 22, wherein the oxide semiconductor layer is formed so that part of the first conductive layer is not overlapped with the oxide semiconductor layer.

29. The method for manufacturing a semiconductor device according to claim 22, wherein the third conductive layer is formed so as to surround the second conductive layer.

30. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over a substrate;

forming a first conductive layer over the oxide semiconductor layer;

forming a second conductive layer over the oxide semiconductor layer, wherein the second conductive layer is not overlapped with the first conductive layer;

forming an insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer;

forming a third conductive layer over the insulating layer, wherein the third conductive layer is formed so as to comprise at least a first portion which is overlapped with neither the first conductive layer nor the second conductive layer.

31. The method for manufacturing a semiconductor device according to claim 30, wherein the third conductive layer is formed so as to be located between the first conductive layer and the second conductive layer.

32. The method for manufacturing a semiconductor device according to claim 30,

further comprising the step of forming a crystal region at an upper superficial portion of the oxide semiconductor layer by heating the oxide semiconductor layer,

wherein the second conductive layer is formed over the crystal region.

33. The method for manufacturing a semiconductor device according to claim 32, wherein the crystal region is formed by heating the oxide semiconductor layer at 500°

C. or higher.

34. The method for manufacturing a semiconductor device according to claim 30, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

35. The method for manufacturing a semiconductor device according to claim 30, wherein the third conductive layer is formed so as to comprise a second portion which is overlapped with the second conductive layer.

36. The method for manufacturing a semiconductor device according to claim 30, wherein the first conductive layer and the second conductive layer is formed on the same surface.

37. The method for manufacturing a semiconductor device according to claim 30, wherein the third conductive layer is formed so as to surround the second conductive layer.