DISPLAY DEVICE

• US 20110069047A1
• Filed: 09/21/2010
• Published: 03/24/2011
• Est. Priority Date: 09/24/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Yamazaki, Shunpei
• Granted Patent: US 9,305,481 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

A display device includes a driver circuit including a logic circuit including a first transistor which is a depletion type transistor and a second transistor which is an enhancement type transistor; a signal line which is electrically connected to the driver circuit; a pixel portion including a pixel whose display state is controlled by input of a signal including image data from the driver circuit through the signal line; a reference voltage line to which reference voltage is applied; and a third transistor which is a depletion type transistor and controls electrical connection between the signal line and the reference voltage line. The first to the third transistors each include an oxide semiconductor layer including a channel formation region.

Claims

1. A display device comprising:

a driver circuit including a logic circuit, the logic circuit including a first transistor which is a depletion type transistor and a second transistor which is an enhancement type transistor;

a signal line;

a pixel portion including a pixel whose display state is configured to be controlled by input of a signal including image data from the driver circuit through the signal line; and

a third transistor which is a depletion type transistor and includes a gate, a source, and a drain,

wherein one of the source and the drain of the third transistor is configured to be supplied with a reference voltage,

wherein the other of the source and the drain of the third transistor is electrically connected to the signal line, and

wherein the gate of the third transistor is configured to be supplied with a gate signal,

wherein the first to third transistors each include an oxide semiconductor layer including a channel formation region.

2. The display device according to claim 1,

wherein the first to third transistors each include:

a gate electrode;

a gate insulating layer over the gate electrode;

the oxide semiconductor layer over the gate insulating layer; and

a first conductive layer and a second conductive layer over parts of the oxide semiconductor layer, the first conductive layer and the second conductive layer each serving as a source electrode or a drain electrode, and

wherein the display device further comprises an oxide insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer.

3. A display device comprising:

a driver circuit including a logic circuit, the logic circuit including a first transistor which is a depletion type transistor and a second transistor which is an enhancement type transistor;

a signal line;

a pixel portion including a pixel whose display state is configured to be controlled by input of a signal including image data from the driver circuit through the signal line; and

a third transistor which is a depletion type transistor and includes a gate, a source, and a drain,

wherein one of the source and the drain of the third transistor is configured to be supplied with a reference voltage,

wherein the other of the source and the drain of the third transistor is electrically connected to the signal line, and

wherein the gate of the third transistor is configured to be supplied with a gate signal,

wherein the first to third transistors each include an oxide semiconductor layer including a channel formation region,

wherein a thickness of the oxide semiconductor layer in the first transistor is larger than a thickness of the oxide semiconductor layer in the second transistor, and

wherein a thickness of the oxide semiconductor layer in the third transistor is larger than a thickness of the oxide semiconductor layer in the second transistor.

4. The display device according to claim 3,

wherein the first to third transistors each include:

a gate electrode;

a gate insulating layer over the gate electrode;

the oxide semiconductor layer over the gate insulating layer; and

a first conductive layer and a second conductive layer over parts of the oxide semiconductor layer, the first conductive layer and the second conductive layer each serving as a source electrode or a drain electrode, and

wherein the display device further comprises an oxide insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer.

5. A display device comprising:

a driver circuit including a logic circuit, the logic circuit including a first transistor which is a depletion type transistor and a second transistor which is an enhancement type transistor;

a signal line;

a pixel portion including a pixel whose display state is configured to be controlled by input of a signal including image data from the driver circuit through the signal line; and

a third transistor which is a depletion type transistor and includes a gate, a source, and a drain,

wherein one of the source and the drain of the third transistor is configured to be supplied with a reference voltage,

wherein the other of the source and the drain of the third transistor is electrically connected to the signal line, and

wherein the gate of the third transistor is configured to be supplied with a gate signal,

wherein the first to third transistors each include a first gate electrode, a second gate electrode, and an oxide semiconductor layer including a channel formation region between the first gate electrode and the second gate electrode.

6. A display device comprising:

a signal line;

a pixel portion including a pixel, the pixel including a first transistor which is an enhancement type transistor and includes a gate, a source, and a drain;

wherein one of the source and the drain of the first transistor is electrically connected to the signal line,

a second transistor which is a depletion type transistor and includes a gate, a source, and a drain,

wherein one of the source and the drain of the second transistor is configured to be supplied with a reference voltage,

wherein the other of the source and the drain of the second transistor is electrically connected to the signal line,

wherein the gate of the second transistor is configured to be supplied with a gate signal, and

wherein the first transistor and the second transistor each include an oxide semiconductor layer including a channel formation region.