METHOD FOR REVERSIBLY MOUNTING A DEVICE WAFER TO A CARRIER SUBSTRATE

• US 20110069467A1
• Filed: 11/22/2010
• Published: 03/24/2011
• Est. Priority Date: 01/24/2008
• Status: Active Grant

• Current Assignee: Brewer Science Inc.
• Original Assignee: Brewer Science Inc.
• Inventors: McCutcheon, Jeremy, Flaim, Tony D.
• Granted Patent: US 9,099,512 B2
• Time in Patent Office: Days
• US Class Current: 361/807
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: Y10T 428/31678 Of metal

Abstract

New temporary bonding methods and articles formed from those methods are provided. The methods comprise bonding a device wafer to a carrier wafer or substrate only at their outer perimeters in order to assist in protecting the device wafer and its device sites during subsequent processing and handling. The edge bonds formed by this method are chemically and thermally resistant, but can also be softened, dissolved, or mechanically disrupted to allow the wafers to be easily separated with very low forces and at or near room temperature at the appropriate stage in the fabrication process.

Claims

1. An article comprising:

a first substrate having front and back surfaces, said front surface having a peripheral region and a central region, wherein said first substrate comprises a device wafer having a device surface comprising an array of devices selected from the group consisting of integrated circuits;

MEMS;

microsensors;

power semiconductors;

light-emitting diodes;

photonic circuits;

interposers;

embedded passive devices; and

microdevices fabricated on or from silicon, silicon-germanium, gallium arsenide, and gallium nitride;

an edge bond bonded to said peripheral region, said edge bond being absent from at least some of said central region so as to form a fill zone; and

a fill material in said fill zone.

2. The article of claim 1, wherein said first substrate comprises a material selected from the group consisting of silicon, sapphire, quartz, metal, glass, and ceramics.

3. The article of claim 1, further comprising a second substrate having a carrier surface, said edge bond being further bonded to said carrier surface.

4. The article of claim 3, wherein said second substrate comprises a material selected from the group consisting of silicon, sapphire, quartz, metal, glass, and ceramics.

5. The article of claim 1, said device surface comprising at least one structure selected from the group consisting of:

solder bumps;

metal posts;

metal pillars; and

structures formed from a material selected from the group consisting of silicon, polysilicon, silicon dioxide, silicon (oxy)nitride, metal, low k dielectrics, polymer dielectrics, metal nitrides, and metal silicides.

6. The article of claim 1, wherein said fill material presents a first surface and a second surface, said article further comprising a second layer in contact with one of said first and second surfaces.

7. The article of claim 6, wherein said second layer is selected from the group consisting of a low adhesive strength layer, a polymeric layer, and a surface modification of said carrier surface or of said device surface.

8. The article of claim 7, wherein said second layer is in contact with said carrier surface.

9. The article of claim 1, wherein said edge bond has a width of from about 2 mm to about 15 mm.

10. The article of claim 1, wherein said edge bond is formed from a material comprising monomers, oligomers, or polymers selected from the group consisting of epoxies, acrylics, silicones, styrenics, vinyl halides, vinyl esters, polyamides, polyimides, polysulfones, polyethersulfones, cyclic olefins, polyolefin rubbers, and polyurethanes.

11. The article of claim 1, wherein said fill material comprises monomers, oligomers, and/or polymers selected from the group consisting of cyclic olefins and amorphous fluoropolymers.

12. An article comprising:

a substrate having front and back surfaces, said front surface having a peripheral region and a central region, wherein said substrate comprises a material selected from the group consisting of silicon, sapphire, quartz, metal, glass, and ceramics; and

a layer of material on said front surface at said central region, said layer being absent from said peripheral region and being selected from the group consisting of a low adhesive strength layer and a surface modification of said front surface.

13. The article of claim 12, wherein said substrate comprises silicon.

14. The article of claim 12, wherein said peripheral region has a width of from about 2 mm to about 15 mm.

15. The article of claim 12, said layer having a thickness of from about 1 nm to about 5 nm.

16. An article comprising:

a first substrate having front and back surfaces, said front surface having a peripheral region and a central region, wherein said first substrate comprises a material selected from the group consisting of silicon, sapphire, quartz, metal, glass, and ceramics;

an edge bond bonded to said peripheral region, said edge bond being absent from at least some of said central region so as to form a fill zone; and

a fill material in said fill zone.

17. The article of claim 16, further comprising a second substrate having a carrier surface, said edge bond being further bonded to said carrier surface.

18. The article of claim 17, wherein said second substrate comprises a material selected from the group consisting of silicon, sapphire, quartz, metal, glass, and ceramics.

19. The article of claim 16, wherein said first substrate comprises a device wafer having a device surface, said device surface comprising at least one structure selected from the group consisting of:

solder bumps;

metal posts;

metal pillars; and

structures formed from a material selected from the group consisting of silicon, polysilicon, silicon dioxide, silicon (oxy)nitride, metal, low k dielectrics, polymer dielectrics, metal nitrides, and metal silicides.

20. The article of claim 16, wherein said fill material presents a first surface and a second surface, said article further comprising a second layer in contact with one of said first and second surfaces.

21. The article of claim 20, wherein said second layer is selected from the group consisting of a low adhesive strength layer, a polymeric layer, and a surface modification of said carrier surface or of said device surface.

22. The article of claim 21, wherein said second layer is in contact with said carrier surface.

23. The article of claim 16, wherein said edge bond has a width of from about 2 mm to about 15 mm.

24. The article of claim 16, wherein said edge bond is formed from a material comprising monomers, oligomers, or polymers selected from the group consisting of epoxies, acrylics, silicones, styrenics, vinyl halides, vinyl esters, polyamides, polyimides, polysulfones, polyethersulfones, cyclic olefins, polyolefin rubbers, and polyurethanes.

25. The article of claim 16, wherein said fill material comprises monomers, oligomers, and/or polymers selected from the group consisting of cyclic olefins and amorphous fluoropolymers.

26. An article comprising:

a first substrate having front and back surfaces, said front surface having a peripheral region and a central region;

an edge bond bonded to said peripheral region, said edge bond being absent from at least some of said central region so as to form a fill zone;

a fill material in said fill zone; and

a second substrate having a carrier surface, said edge bond being further bonded to said carrier surface.

27. The article of claim 26, wherein said second substrate comprises a material selected from the group consisting of silicon, sapphire, quartz, metal, glass, and ceramics.

28. The article of claim 26, wherein said first substrate comprises a device wafer having a device surface, said device surface comprising at least one structure selected from the group consisting of:

solder bumps;

metal posts;

metal pillars; and

structures formed from a material selected from the group consisting of silicon, polysilicon, silicon dioxide, silicon (oxy)nitride, metal, low k dielectrics, polymer dielectrics, metal nitrides, and metal silicides.

29. The article of claim 26, wherein said fill material presents a first surface and a second surface, said article further comprising a second layer in contact with one of said first and second surfaces.

30. The article of claim 29, wherein said second layer is selected from the group consisting of a low adhesive strength layer, a polymeric layer, and a surface modification of said carrier surface or of said device surface.

31. The article of claim 30, wherein said second layer is in contact with said carrier surface.

32. The article of claim 26, wherein said edge bond has a width of from about 2 mm to about 15 mm.

33. The article of claim 26, wherein said edge bond is formed from a material comprising monomers, oligomers, or polymers selected from the group consisting of epoxies, acrylics, silicones, styrenics, vinyl halides, vinyl esters, polyamides, polyimides, polysulfones, polyethersulfones, cyclic olefins, polyolefin rubbers, and polyurethanes.

34. The article of claim 26, wherein said fill material comprises monomers, oligomers, and/or polymers selected from the group consisting of cyclic olefins and amorphous fluoropolymers.