Non-Volatile Semiconductor Memory with Page Erase

• US 20110069551A1
• Filed: 09/22/2010
• Published: 03/24/2011
• Est. Priority Date: 03/29/2006
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki
• Granted Patent: US 7,995,401 B2
• Time in Patent Office: Days
• US Class Current: 365/185.12
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.

Claims

1. A method of erasing a page in a nonvolatile memory array having plural strings of memory cells on a substrate, wordlines across the strings to pages of memory cells and a pass transistor applying a voltage to each wordline, the method comprising:

in each unselected block, disabling each pass transistor;

in each selected block;

enabling each pass transistor;

at each of the plural selected wordlines of the selected block, applying a select voltage to the pass transistor; and

at each of plural unselected wordlines of the selected block,

applying an unselect voltage to the pass transistor; and

applying a substrate voltage to the substrate of the selected and unselected blocks;

each wordline of each unselected block floating to prevent erasure, a resulting voltage of each selected wordline being substantially the same as the select voltage and causing the page of memory cells of the selected wordline to erase, and a resulting voltage of each unselected wordline being substantially the same as the unselect voltage and preventing erasure of the page of memory cells of the unselected wordline.

2. A method as recited in claim 1 wherein the select voltage and the unselect voltage are applied to the pass transistors of the selected block through a wordline decoder adapted to apply the select voltage to any of the pass transistors as the unselect voltage is applied to any other pass transistor.

3. A method as recited in claim 1 wherein the selected wordlines include selected wordlines separated by at least one unselected wordline.

4. A method as recited in claim 1 wherein the unselected wordlines include unselected wordlines separated by at least one selected wordline.

5. A method as recited in claim 1 wherein the select voltage is about zero volts and the unselect voltage is about equal to the applied substrate voltage.

6. A method as recited in claim 1 wherein the unselect voltage is closer to the voltage applied to the substrate than to the select voltage.

7. A nonvolatile memory comprising:

a memory array comprising plural strings of memory cells on a substrate and wordlines across the strings to pages of memory cells;

a pass transistor to each wordline;

decoder circuitry that responds to address instructions in an erase operation to;

disable each pass transistor in an unselected block;

enable each pass transistor in a selected block;

apply a select voltage to each pass transistor of one or more pages to be erased in the selected block; and

apply an unselect voltage to each transistor of one or more pages not to be erased in the selected block; and

a substrate voltage source that applies a voltage to the substrate during the erase operation;

each wordline of each unselected block floating to prevent erasure, a resulting voltage of each selected wordline being substantially the same as the select voltage and causing the page of memory cells of the selected wordline to erase, a resulting voltage of each unselected wordline being substantially the same as the unselect voltage and preventing erasure of the page of memory cells of the unselected wordline.

8. A memory as recited in claim 7, wherein the wordline decoder is adapted to apply the select voltage to any of the wordlines and the unselect voltage to any of the wordlines.

9. A memory as recited in claim 7 wherein the select voltage is about zero volts and the unselect voltage is about equal to the voltage.

10. A memory as recited in claim 7 wherein the unselect voltage is closer to the erase voltage applied to the substrate than to the select voltage.