SEMICONDUCTOR MEMORY DEVICE

• US 20110069574A1
• Filed: 03/08/2010
• Published: 03/24/2011
• Est. Priority Date: 09/18/2009
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: HIRABAYASHI, Osamu
• Application Number:
  US12/719,707
• Publication Number:
  US 20110069574A1
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Abstract

A semiconductor memory device includes a memory cell array, a word line driver, and a bit line booster. The memory cell array has multiple word lines WL, multiple bit line pairs BL, and multiple memory cells MC provided at the respective intersections of the word lines WL and the bit line pairs BL. The word line driver drives a selected word line WL to a positive voltage VWL when data is written to the memory cells MC. The bit line booster drives a selected bit line pair BL to a negative voltage VBL corresponding to the voltage VWL when data is written to the memory cells MC.

Claims

1. A semiconductor memory device comprising:

a memory cell array comprising a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of memory cells connected to the intersections of the plurality of word lines and the plurality of bit lines;

a word line driver configured to drive a selected word line to a positive first voltage when data is written to the memory cells; and

a bit line driver configured to drive a selected bit line to a negative second voltage corresponding to the first voltage when the data is written to the memory cells.

2. The semiconductor memory device of claim 1, wherein each memory cell comprises an SRAM cell comprising a data retention module, and a transfer transistor connected between the data retention module and one of the bit lines, the transfer transistor comprising a gate connected to one of the word lines.

3. The semiconductor memory device of claim 1, wherein the word line driver and the bit line driver are configured to output the first voltage and the second voltage higher than the first voltage, respectively, depending on characteristics of the memory cell, and

4. The semiconductor memory device of claim 1, further comprising:

a voltage setting module configured to store voltage setting information associated with the first voltage and the second voltage, wherein

the world line driver configured to generate the first voltage based on the voltage setting information; and

the bit line driver configured to generate the second voltage based on the voltage setting information.

5. The semiconductor memory device of claim 4, wherein the voltage setting module comprises a fuse circuit configured to store the voltage setting information.

6. The semiconductor memory device of claim 4, wherein

the word line driver comprises:

an inverter circuit comprising a P-channel insulated gate field effect transistor and an N-channel insulated gate field effect transistor; and

a step-down module connected to an output terminal of the inverter circuit, and

the word line driver is configured to adjust a resistance value of the step-down module based on the voltage setting information, and to output a midpoint potential between a supply voltage and a ground voltage as the first voltage with the P-channel insulated gate field effect transistor and the step-down module, when a word line is selected.

7. The semiconductor memory device of claim 6, wherein the P-channel insulated gate field effect transistor and the N-channel insulated gate field effect transistor are either Metal-Oxide-Semiconductor (MOS) transistors or Metal-Insulator-Semiconductor (MIS) transistors.

8. The semiconductor memory device of claim 4, wherein

the bit line driver comprises a bootstrap circuit which is a negative potential generator,

the bootstrap circuit comprises a capacitor and a charging or discharging circuit connected to a first end of the capacitor, and configured to adjust the second voltage on the first end of the capacitor when a second end of the capacitor is inverted from a high level to a low level, by adjusting a charging current of the charging circuit or a discharging current of the discharging circuit based on the voltage setting information.

9. A semiconductor memory device, comprising:

a memory cell array comprising a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of memory cells connected to the intersections of the plurality of word lines and the plurality of bit lines;

a word line driver configured to drive a selected word line to a positive first voltage when data is written to the memory cell; and

a bit line driver configured to drive a selected bit line to a negative second voltage corresponding to the first voltage when the data is written to the memory cell,

wherein the word line driver comprises;

an inverter circuit comprising a first P-channel insulated gate field effect transistor and a first N-channel insulated gate field effect transistor; and

a step-down module connected to an output terminal of the inverter circuit, and

wherein the word line driver is configured to output a midpoint potential between a supply voltage and a ground voltage as the first voltage with the first P-channel insulated gate field effect transistor and the step-down module when a word line is selected.

10. The semiconductor memory device of claim 9, wherein each memory cell comprises an SRAM cell comprising a data retention module, and a transfer transistor connected between the data retention module and one of the bit lines, the transfer transistor comprising a gate connected to one of the word lines.

11. The semiconductor memory device of claim 10, wherein the first P-channel insulated gate field effect transistor and the first N-channel insulated gate field effect transistor are either MOS transistors or MIS transistors.

12. The semiconductor memory device of claim 9, wherein the step-down module comprises a second P-channel insulated gate field effect transistor between the output terminal of the inverter circuit and the ground potential.

13. The semiconductor memory device of claim 9, wherein the step-down module comprises the second P-channel insulated gate field effect transistor and a resistance connected in series between the output terminal of the inverter circuit and the ground potential.

14. The semiconductor memory device of claim 9, wherein

the bit line driver comprises a bootstrap circuit which is a negative potential generator,

the bootstrap circuit comprises a capacitor and a charging or discharging circuit connected to a first end of the capacitor, and configured to adjust the second voltage on the first end of the capacitor when a second end of the capacitor is inverted from a high level to a low level, by adjusting a charging current of the charging circuit or a discharging current of the discharging circuit based on the voltage setting information.

15. A semiconductor memory device, comprising:

a regulator configured to step down a supply voltage and to generate a positive first voltage; and

a memory block configured to receive the first voltage from the regulator in order to write data and to read data, wherein

the memory block comprises;

a memory cell array comprising a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of memory cells connected to the intersections of the plurality of word lines and the plurality of bit lines;

a word line driver configured to drive a selected word line to the positive first voltage when data is written to the memory cells; and

a bit line driver configured to drive a selected bit line to a negative second voltage corresponding to the first voltage when the data is written to the memory cells.

16. The semiconductor memory device of claim 15, wherein each memory cell comprises an SRAM cell comprising a data retention module, and a transfer transistor connected between the data retention module and one of the bit lines, the transfer transistor comprising a gate connected to one of the word lines.

17. The semiconductor memory device of claim 15, wherein the word line driver and the bit line driver are configured to output the positive first voltage and the negative second voltage higher than the positive first voltage respectively, depending on characteristics of the memory cell.