DRIVER CIRCUIT, DISPLAY DEVICE INCLUDING THE DRIVER CIRCUIT, AND ELECTRONIC APPLIANCE INCLUDING THE DISPLAY DEVICE

• US 20110069805A1
• Filed: 09/22/2010
• Published: 03/24/2011
• Est. Priority Date: 09/24/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KOYAMA, Jun, MIYAKE, Hiroyuki
• Granted Patent: US 8,243,873 B2
• Time in Patent Office: Days
• US Class Current: 377/2
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H03K 17/002 Switching arrangements with several input- or output terminals code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit.

Claims

1. A driver circuit comprising:

a static shift register comprising an inverter circuit and a switch,

wherein the inverter circuit comprises a first transistor and a second transistor,

wherein the switch comprises a third transistor,

wherein the first to third transistors each comprise an oxide semiconductor layer and are depletion-mode transistors, and

wherein an amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit.

2. The driver circuit according to claim 1,

wherein the clock signals are a first clock signal and a second clock signal, and

wherein the second clock signal is an inverted signal of the first clock signal.

3. The driver circuit according to claim 1, wherein an L/W ratio of the first transistor is higher than an L/W ratio of the second transistor.

4. The driver circuit according to claim 1, wherein a film thickness of a semiconductor layer of the first transistor is larger than a film thickness of a semiconductor layer of the second transistor.

5. The driver circuit according to claim 1, wherein the first to third transistor are n-channel transistors.

6. A display device comprising the driver circuit according to claim 1.

7. An electronic appliance comprising the display device according to claim 6.

8. A driver circuit comprising:

a static shift register comprising an inverter circuit and a switch; and

a demultiplexer circuit connected to an output terminal of the shift register,

wherein the inverter circuit comprises a first transistor and a second transistor,

wherein the switch comprises a third transistor,

wherein the first to third transistors each comprise an oxide semiconductor layer and are depletion-mode transistors,

wherein an amplitude voltage of clock signals for driving the first transistor is higher than a power supply voltage for driving the inverter circuit, and

wherein output terminals of the demultiplexer circuit are each connected to a fourth transistor for holding a potential of the output terminal.

9. The driver circuit according to claim 8,

wherein the clock signals are a first clock signal and a second clock signal, and

wherein the second clock signal is an inverted signal of the first clock signal.

10. The driver circuit according to claim 8, wherein an L/W ratio of the first transistor is higher than an L/W ratio of the second transistor.

11. The driver circuit according to claim 8, wherein a film thickness of a semiconductor layer of the first transistor is larger than a film thickness of a semiconductor layer of the second transistor.

12. The driver circuit according to claim 8, wherein an L/W ratio of a fifth transistor in the demultiplexer circuit is lower than an L/W ratio of the fourth transistor.

13. The driver circuit according to claim 8,

wherein a gate of the fourth transistor is electrically connected to a line through which a positive power supply voltage is supplied,

wherein a first terminal of the fourth transistor is electrically connected to a line through which a negative power supply voltage is supplied, and

wherein a second terminal of the fourth transistor is electrically connected to an output terminal of the demultiplexer circuit.

14. The driver circuit according to claim 8, wherein the first to fourth transistor are n-channel transistors.

15. A display device comprising the driver circuit according to claim 8.

16. An electronic appliance comprising the display device according to claim 15.

17. A method for driving a driver circuit, the driver circuit including a static shift register comprising an inverter circuit and a switch,

wherein the inverter circuit comprises a first transistor and a second transistor,

wherein the switch comprises a third transistor, and

wherein the first to third transistors each comprise an oxide semiconductor layer and are depletion-mode transistors,

said method comprising the step of:

inputting clock signals to the switch,

wherein an amplitude voltage of the clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit.

18. The driver circuit according to claim 17,

wherein the clock signals are a first clock signal and a second clock signal, and

wherein the second clock signal is an inverted signal of the first clock signal.

19. The driver circuit according to claim 17, wherein an L/W ratio of the first transistor is higher than an L/W ratio of the second transistor.

20. The driver circuit according to claim 17, wherein a film thickness of a semiconductor layer of the first transistor is larger than a film thickness of a semiconductor layer of the second transistor.

21. The driver circuit according to claim 17, wherein the first to third transistor are n-channel transistors.

22. A display device comprising the driver circuit according to claim 17.

23. An electronic appliance comprising the display device according to claim 22.