METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

• US 20110070702A1
• Filed: 09/21/2009
• Published: 03/24/2011
• Est. Priority Date: 09/21/2009
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Yeh, Chiu-Hsien, Chien, Chin-Cheng, Lin, Chun-Hsien
• Granted Patent: US 8,232,154 B2
• Time in Patent Office: Days
• US Class Current: 438/211
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method for fabricating a semiconductor device is provided. A high dielectric constant (high-k) layer and a work function metal layer are formed in sequence on a substrate. A hard mask layer is formed on the work function metal layer, where the material of the hard mask layer is lanthanum oxide. The work function metal layer is patterned by using the hard mask layer as a mask. The hard mask layer is then removed. Afterwards, a gate structure is formed on the substrate.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a high dielectric constant layer and a work function metal layer in sequence on a substrate;

forming a hard mask layer on the work function metal layer, wherein the hard mask layer comprises lanthanum oxide;

patterning the work function metal layer by using the hard mask layer as a mask;

removing the hard mask layer; and

forming a gate structure on the substrate.

2. The method of fabricating the semiconductor device as claimed in claim 1, wherein the step of forming the work function metal layer comprises:

forming a cap layer on the high dielectric constant layer; and

forming a metal layer on the cap layer.

3. The method of fabricating the semiconductor device as claimed in claim 2, wherein the cap layer comprises a material selected from the group consisting of Al₂O₃, Ga₂O₃, In₂O₃, Ti₂O₃, La₂O₃, Dy₂O₃, Y₂O₃, MgO₂, and an oxide of an element in a lanthanide series.

4. The method of fabricating the semiconductor device as claimed in claim 2, wherein the metal layer comprises a material selected from the group consisting of TiN, TaN, TaC, TaCNO, TaCN, and TiAl_x.

5. The method of fabricating the semiconductor device as claimed in claim 1, wherein before forming the high dielectric constant layer, the method further comprises forming an insulation layer on the substrate.

6. A method of fabricating a semiconductor device, comprising:

providing a substrate, having a first region and a second region disposed separately;

forming a gate dielectric layer and a first work function metal layer in sequence on the substrate;

forming a first hard mask layer on the first work function metal layer in the first region, wherein the first hard mask layer comprises lanthanum oxide;

removing the first work function metal layer in the second region by using the first hard mask layer as a mask;

forming a second work function metal layer on the substrate;

forming a second hard mask layer on the second work function metal layer in the second region, wherein the second hard mask layer comprises lanthanum oxide;

removing the second work function metal layer in the first region by using the second hard mask layer as a mask; and

removing the second hard mask layer.

7. The method of fabricating the semiconductor device as claimed in claim 6, before forming the second work function metal layer, further comprising removing the first hard mask layer.

8. The method of fabricating the semiconductor device as claimed in claim 6, wherein the second work function metal layer covers the first hard mask layer.

9. The method of fabricating the semiconductor device as claimed in claim 8, wherein the first hard mask layer is removed while the second hard mask layer is being removed.

10. The method of fabricating the semiconductor device as claimed in claim 6, wherein the step of forming the first work function metal layer comprises:

forming a first cap layer on the gate dielectric layer in the first region and the second region; and

forming a first metal layer on the first cap layer.

11. The method of fabricating the semiconductor device as claimed in claim 10, wherein the first metal layer comprises a material selected from the group consisting of TiN, TaN, TaC, TaCNO, TaCN, and TiAl_x.

12. The method of fabricating the semiconductor device as claimed in claim 10, wherein the step of forming the second work function metal layer comprises:

forming a second cap layer on the first work function metal layer in the first region and on the gate dielectric layer in the second region; and

forming a second metal layer on the second cap layer.

13. The method of fabricating the semiconductor device as claimed in claim 12, wherein the second metal layer comprises a material selected from the group consisting of TiN, TaN, TaC, TaCNO, TaCN, and TiAl_x.

14. The method of fabricating the semiconductor device as claimed in claim 12, wherein when the first region is a P-type metal oxide semiconductor region and the second region is an N-type metal oxide semiconductor region, the first cap layer comprises aluminum oxide and the second cap layer comprises lanthanum oxide.

15. The method of fabricating the semiconductor device as claimed in claim 14, wherein the second cap layer in the first region is removed while the second hard mask layer is being removed.

16. The method of fabricating the semiconductor device as claimed in claim 12, wherein when the first region is an N-type metal oxide semiconductor region and the second region is a P-type metal oxide semiconductor region, the first cap layer comprises lanthanum oxide and the second cap layer comprises aluminum oxide.

17. The method of fabricating the semiconductor device as claimed in claim 6, wherein the step of forming the gate dielectric layer comprises:

forming an insulation layer on the substrate; and

forming a high dielectric constant layer on the insulation layer.

18. The method of fabricating the semiconductor device as claimed in claim 6, further comprising:

forming a conductive layer on the first work function metal layer and the second work function metal layer;

patterning the conductive layer, the first work function metal layer, the second work function metal layer, and the gate dielectric layer, so as to form a first gate structure in the first region and a second gate structure in the second region; and

forming a first source/drain region in the substrate at respective sides of the first gate structure, and forming a second source/drain region in the substrate at respective sides of the second gate structure.

19. The method of fabricating the semiconductor device as claimed in claim 18, after forming the first gate structure and the second gate structure and before forming the first source/drain region and the second source/drain region, further comprising forming a spacer on each sidewall of the first gate structure and the second gate structure respectively.

20. The method of fabricating the semiconductor device as claimed in claim 18, wherein after forming the first source/drain region and the second source/drain region, the method further comprises forming a stress layer on the substrate to cover the first gate structure and the second gate structure.