Method for forming NAND typed memory device

• US 20110070706A1
• Filed: 11/30/2010
• Published: 03/24/2011
• Est. Priority Date: 11/07/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Woo, Won Sic, Kim, Nam-Kyeong
• Granted Patent: US 8,163,614 B2
• Time in Patent Office: Days
• US Class Current: 438/258
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconductor substrate, etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer, forming a low resistance layer in the opening, forming a control gate conductive layer over the semiconductor substrate, and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer to form gate stacks of memory cells and source/drain select transistors.

Claims

1. A method for fabricating a NAND type flash memory device comprising:

defining a select transistor region and a memory cell region in a semiconductor substrate;

forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over the semiconductor substrate;

etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer in the select transistor region;

forming a low resistance layer in the opening;

forming a control gate conductive layer over the semiconductor substrate; and

etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer, thereby forming gate stacks of memory cells and source/drain select transistors.

2. The method according to claim 1, wherein at least one of the floating gate conductive layer and the control gate conductive layer comprises a polysilicon layer.

3. The method according to claim 1, further comprising forming a buffer layer over the dielectric layer prior to forming the opening.

4. The method according to claim 3, wherein the buffer layer comprises a polysilicon layer.

5. The method according to claim 1, further comprising forming a spacer on the sidewalls of the opening after forming the opening.

6. The method according to claim 5, wherein the spacer comprises a polysilicon layer.

7. The method according to claim 5, further comprising etching the exposed floating gate conductive layer to recess the floating gate conductive layer after forming the spacer

8. The method according to claim 1, wherein the low resistance layer comprises a metal silicide layer.

9. The method according to claim 1, wherein forming the low resistance layer comprises:

depositing a metal selected from the group consisting of titanium (Ti), cobalt (Co), tantalum (Ta), niobium (Nb), and platinum (Pt); and

heat treating the low resistance layer to form the metal silicide layer.

10. The method according to claim 1, further comprising forming a barrier metal layer in the remaining region of the opening after forming the low resistance layer.

11. The method according to claim 10, wherein the barrier metal layer is selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and tungsten (W).

12. The method according to claim 1, comprising forming the low resistance layer over the sidewalls and the bottom of the opening.