Method for making trench MOSFET with shallow trench structures

• US 20110070708A1
• Filed: 09/21/2009
• Published: 03/24/2011
• Est. Priority Date: 09/21/2009
• Status: Active Grant

• Current Assignee: Memoir Systems, Inc (Cisco Systems, Inc.), Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hsieh, Fu-Yuan
• Granted Patent: US 8,105,903 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for making trench MOSFET with shallow trench structures with thick trench bottom is disclosed. The improved method resolves the problem of deterioration of breakdown voltage resulted by LOCOS having a bird'"'"'s beak shape introduced in prior art, and at the same time, the inventive device has a lower Qgd and lower Rds.

Claims

1. A method for making trench MOSFET with shallow trench structures comprising method for making a plurality of gate trenches within epitaxial layer, wherein further comprising:

depositing a first insulation layer along the inner surface of said plurality of gate trenches and the top surface of said epitaxial layer;

depositing a layer of un-doped poly or amorphous silicon onto said first insulation layer;

depositing an nitride layer onto said un-doped poly or amorphous silicon and carrying out nitride anisotropic etching to leave said nitride layer only on sidewalls of said plurality of gate trenches;

oxidizing said un-doped poly or amorphous silicon on bottom of said plurality of gate trenches and the top surface of said epitaxial layer;

removing said nitride layer from the sidewalls of said plurality of gate trenches.

2. The method of claim 1, wherein said un-doped poly silicon is deposited at 650°

C. or above.

3. The method of claim 1, wherein said un-doped amorphous silicon is deposited below 650°

C.

4. The method of claim 1, wherein making a plurality of gate trenches within epitaxial layer further comprising:

depositing a layer of hard mask covering said epitaxial layer over a substrate layer;

applying a trench mask onto said hard mask and etching said hard mask and said epitaxial layer for the formation of said plurality of gate trenches;

forming a sacrificial oxide along the inner surface of said plurality of gate trenches and then removing said sacrificial oxide;

growing a screen oxide along the inner surface of said plurality of gate trenches and carrying out ion implantation for the formation of regions around the bottom of said plurality of gate trenches with doping concentration heavier than said epitaxial layer;

removing said screen oxide and said hard mask.

5. The method of claim 1, wherein making a plurality of gate trenches within epitaxial layer further comprising:

depositing a layer of hard mask covering epitaxial layer over a substrate layer;

applying a trench mask onto said hard mask and etching said hard mask and said epitaxial layer for the formation of plurality of gate trenches;

removing said hard mask;

forming a sacrificial oxide along the inner surface of said plurality of gate trenches and then removing said sacrificial oxide;

growing a screen oxide along the inner surface of said plurality of gate trenches and carrying out ion implantation for the formation of regions around the bottom of said plurality of gate trenches and near the top surface of said epitaxial layer with doping concentration heavier than said epitaxial layer;

removing said screen oxide.

6. The method of claim 1 further comprising:

depositing doped poly or combination of doped poly and non-doped poly to fill said gate trenches and then etching back to form a plurality of shallow trenched gates after the formation of thick trench bottom and forming silicide on top poly as alternative.

7. The method of claim 6 further comprising:

applying a body mask;

carrying out body dopant ion implantation and driving-in body dopant to form body region;

etching back the oxide on top surface of said epitaxial layer to 100˜

400 Å

;

applying a source mask;

carrying out source dopant ion implantation.

8. The method of claim 7 further comprising:

depositing a second insulation layer covering the top surface of said epitaxial layer and said plurality of shallow trenched gates and applying a source-body contact mask whereon;

etching through said second insulation layer and said source region, and into said body region to form source-body contact trenches;

applying a gate contact mask and etching through said second insulation layer and into poly-silicon to form gate contact trenches;

carrying out body contact dopant ion implantation to form body contact region underneath each source-body contact trench and activating said body contact dopant by RTA;

depositing a barrier layer of Ti/TiN or Co/TiN or Ta/TiN and W metal successively and then etching back to form metal plug in each of said source-body contact trenches and said gate contact trench;

depositing a resistance-reduction layer Ti or TiN and Al alloys or Cu and patterning by applying a metal mask to form source metal and gate metal.

9. The method of claim 7 further comprising applying a guard ring mask and carrying out ion implantation to form guard ring before applying said body mask.

10. The method of claim 7 further comprising driving-in source dopant after said source dopant ion implantation.

11. The method of claim 8, wherein said gate metal also serves as field metal plate beyond body region and overlap said epitaxial layer ranging from 2 to 10 μ

m.

12. A method for making trench MOSFET with shallow trench structures comprising:

depositing a layer of hard mask covering said epitaxial layer over a substrate layer;

applying a trench mask onto said hard mask and etching said hard mask and said epitaxial layer for the formation of said plurality of gate trenches;

forming a sacrificial oxide along the inner surface of said plurality of gate trenches and then removing said sacrificial oxide;

growing a screen oxide along the inner surface of said plurality of gate trenches and carrying out ion implantation for the formation of regions around the bottom of said plurality of gate trenches with doping concentration heavier than said epitaxial layer;

removing said screen oxide and said hard mask;

depositing a first insulation layer as gate oxide along the inner surface of said plurality of gate trenches and the top surface of said epitaxial layer;

depositing a layer of un-doped poly or amorphous silicon onto said first insulation layer;

depositing an nitride layer onto said un-doped poly or amorphous silicon and carrying out nitride anisotropic etching to leave said nitride layer only on sidewalls of said plurality of gate trenches;

oxidizing said un-doped poly or amorphous silicon on bottom of said gate trenches and the top surface of said epitaxial layer.

removing said nitride layer from the sidewalls of said plurality of gate trenches.

13. A method for making trench MOSFET with shallow trench structures comprising:

depositing a layer of hard mask covering said epitaxial layer over a substrate;

applying a trench mask onto said hard mask and etching said hard mask and said epitaxial layer for the formation of said plurality of gate trenches;

forming a sacrificial oxide along the inner surface of said plurality of gate trenches and then removing said sacrificial oxide;

growing a screen oxide along the inner surface of said plurality of gate trenches and carrying out ion implantation for the formation of regions around the bottom of said plurality of gate trenches with doping concentration heavier than said epitaxial layer;

removing said screen oxide and said hard mask;

depositing a first insulation layer along the inner surface of said plurality of gate trenches and the top surface of said epitaxial layer;

depositing a layer of un-doped poly or amorphous silicon onto said first insulation layer;

depositing an nitride layer onto said un-doped poly or amorphous silicon and carrying out nitride anisotropic etching to leave said nitride layer only on sidewalls of said plurality of gate trenches;

oxidizing said un-doped poly or amorphous silicon on bottom of said plurality of gate trenches and the top surface of said epitaxial layer;

removing said nitride layer from the sidewalls of said plurality of gate trenches;

depositing doped poly or combination of doped poly and non-doped poly to fill said plurality of gate trenches and then etching back to form a plurality of shallow trenched gates;

applying a body mask and carrying out body dopant ion implantation and driving-in said body dopant to form body region;

applying a source mask and carrying out source dopant ion implantation to form source region.

depositing a second insulation layer covering the top surface of said epitaxial layer and said plurality of shallow trenched gates and applying a source-body contact mask whereon;

etching through said second insulation layer and said source region, and into said body region to form source-body contact trenches;

applying a gate contact mask and etching through said second insulation layer and into said doped poly to form gate contact trenches.