PCI EXPRESS ENHANCEMENTS AND EXTENSIONS
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Abstract
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
68 Citations
91 Claims
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1-40. -40. (canceled)
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41. A method comprising:
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receiving a first number of transactions on a serial point-to-point interconnect in a first order; determining a second order of the plurality of transactions, the second order to be based at least in part on maintaining a priority of a plurality transactions of the first number of transactions that each reference a first memory location, wherein the second order is different from the first order. - View Dependent Claims (42, 43, 44, 45, 46)
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47. An apparatus comprising:
a controller including; an input/output (I/O) module comprising a protocol stack to receive a first number of transactions in a first order, and a re-order module coupled to the I/O module to re-order the first number of transactions to a second order, which is different from the first order, based at least in part on not allowing a plurality of corresponding transactions of the first number of transactions to pass each other in the second order. - View Dependent Claims (48, 49, 50, 51)
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52. A system comprising:
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a device including a first layered protocol stack, the first layered protocol stack including a first physical layer, a first link layer, and a first transaction layer, wherein the first layered protocol stack is to transmit a first number of transactions to a controller hub over a serial point-to-point link; the controller hub coupled to the device through the serial point-to-point link including; a second layered protocol stack, the second layered protocol stack including a second physical layer, a second link layer, and a second transaction layer, wherein the second layered protocol stack is to receive the first number of transactions in a first order, re-order logic to re-order the first number of transactions into a second order based at least in part on preserving a priority of a plurality of corresponding transactions of the first number of transactions that reference a same memory location, wherein the second order is different from the first order; and servicing logic to service the first number of transactions in the second order. - View Dependent Claims (54, 55)
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53. (canceled)
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56-82. -82. (canceled)
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83. A method comprising:
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receiving, with a controller, a plurality of transactions in a first order from a device coupled to the controller through a serial point-to-point interconnect, wherein the controller includes a layered protocol stack; determining, with a re-order module of the controller, a second order of the plurality of transactions at least in part based on not allowing a first transaction of the plurality of transactions referencing a memory address to be ordered after a second transaction of the plurality of transactions referencing said memory address in the second order, wherein the first transaction precedes the second transaction in the first order; and servicing the plurality of transactions in the second order in response to determining the second order. - View Dependent Claims (84, 85, 86)
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87. An apparatus comprising:
a controller hub adapted to be coupled to a graphics processing device through a serial interconnect, the controller hub comprising; an input/output (I/O) module comprising a protocol stack adapted to receive a first number of transactions in a first order from the graphics processing device, the protocol stack including a physical layer, a link layer, and a transaction layer; and a re-order module coupled to the I/O module, the re-order module adapted to re-order the first number of transactions to a second order, which is different from the first order, based at least in part on not allowing a plurality of transactions of the first number of transactions that reference the same memory address to pass each other in the second order. - View Dependent Claims (88, 89, 90, 91)
Specification