INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY

• US 20110072213A1
• Filed: 09/22/2010
• Published: 03/24/2011
• Est. Priority Date: 09/23/2009
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Shebanow, Michael C., NICKOLLS, John R., Coon, Brett W.
• Granted Patent: US 9,639,479 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

A method for managing a parallel cache hierarchy in a processing unit. The method includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.

Claims

1. A method for managing a parallel cache hierarchy in a processing unit, the method comprising:

receiving an instruction from a scheduler unit, wherein the instruction comprises a load instruction or a store instruction;

determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and

executing the instruction and caching the data associated with the instruction based on the cache operations modifier.

2. The method of claim 1, wherein the instruction is further associated with an address that identifies a memory region, wherein the policy for caching data is based on the memory region.

3. The method of claim 2, wherein the data is cached if the address is in a local memory region, and is not cached if the address is in a global region.

4. The method of claim 1, wherein the parallel cache hierarchy includes an L1 cache level and an L2 cache level.

5. The method of claim 4, wherein each processor included in the processing unit includes a different L1 cache at the L1 cache level, the L2 cache level includes at least one L2 cache that each processor is configured to access.

6. The method of claim 4, wherein the cache operations modifier is implemented to cause the data associated with the instruction to be cached at both the L1 cache level and the L2 cache level.

7. The method of claim 6, wherein the data associated with the instruction is cached at each of the L1 cache level and the L2 cache level with an evict-first eviction policy.

8. The method of claim 4, wherein the cache operations modifier is implemented to invalidate and discard the data cached in the L1 cache following a load instruction.

9. The method of claim 4, wherein the cache operations modifier is implemented to cause the data associated with the instruction to be cached at the L2 cache level and not cached at the L1 cache level.

10. The method of claim 9, wherein the data associated with the instruction is cached at the L2 cache level with an evict-first eviction policy.

11. The method of claim 1, wherein the cache operations modifier is implemented to cause data associated with a store instruction to be cached with a write-back policy or a write-through policy.

12. The method of claim 1, wherein the cache operations modifier is implemented to cause data associated with a load instruction to be cached with a volatile fetch-always policy.

13. A system for managing a parallel cache hierarchy, the system comprising:

a processor, configured to;

receive an instruction that comprises a load instruction or a store instruction,

determine that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy, and

execute the instruction and cache the data associated with the instruction based on the cache operations modifier.

14. The system of claim 13, wherein the instruction is further associated with an address that identifies a memory region, wherein the policy for caching data is based on the memory region.

15. The system of claim 14, wherein the data is cached if the address is in a local memory region, and is not cached if the address is in a global region.

16. The system of claim 13, wherein the parallel cache hierarchy includes an L1 cache level and an L2 cache level.

17. The system of claim 16, wherein each processor included in the processing unit includes a different L1 cache at the L1 cache level, the L2 cache level includes at least one L2 cache that each processor is configured to access.

18. The system of claim 16, wherein the cache operations modifier is implemented to cause the data associated with the instruction to be cached at both the L1 cache level and the L2 cache level.

19. The system of claim 18, wherein the data associated with the instruction is cached at each of the L1 cache level and the L2 cache level with an evict-first eviction policy.

20. The system of claim 16, wherein the cache operations modifier is implemented to invalidate and discard the data cached in the L1 cache following a load instruction.

21. The system of claim 16, wherein the cache operations modifier is implemented to cause the data associated with the instruction to be cached at the L2 cache level and not cached at the L1 cache level.

22. The system of claim 21, wherein the data associated with the instruction is cached at the L2 cache level with an evict-first eviction policy.

23. The system of claim 13, wherein the cache operations modifier is implemented to cause data associated with a store instruction to be cached with a write-back policy or a write-through policy.

24. The system of claim 13, wherein the cache operations modifier is implemented to cause data associated with a load instruction to be cached with a volatile fetch-always policy.