TEARING-PROOF METHOD FOR WRITING DATA IN A NONVOLATILE MEMORY

• US 20110072300A1
• Filed: 09/21/2010
• Published: 03/24/2011
• Est. Priority Date: 09/21/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Rousseau, Hubert
• Granted Patent: US 8,499,192 B2
• Time in Patent Office: Days
• US Class Current: 714/6.1
• CPC Class Codes: G06F 11/1435 using file system or storage system metadata
• CPC Class Codes: G06F 11/1471 involving logging of persistent data for recovery
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written

Abstract

A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone.

Claims

1. A method for writing and reading data in electrically erasable and programmable nonvolatile memory cells comprising:

writing data in a block of a first nonvolatile memory zone that is programmable by block;

in conjunction with the writing the data in the block of the first nonvolatile memory zone, writing in a second nonvolatile memory zone containing metadata associated with data in the first nonvolatile memory zone, metadata associated with the writing of the data in the block, the metadata being written in a temporary information structure associated with the writing of the data in the block, wherein the temporary information structure associated with the writing of the data in the block includes;

a start flag;

an identifier of the temporary information structure;

an information about a location of the block in the first nonvolatile memory zone; and

a final flag; and

in conjunction with a power-on of the first nonvolatile memory zone, searching for an anomaly in temporary information structures present in the second nonvolatile memory zone.

2. The method of claim 1 comprising detecting an anomaly in a temporary information structure present in the second nonvolatile memory zone based on flags of the temporary information structure present in the second nonvolatile memory zone not having a same logic state, the logic state being a state of erased or written.

3. The method of claim 1 comprising:

upon a detection of an anomaly in an erroneous temporary information structure present in the second nonvolatile memory zone;

recopying the erroneous temporary information structure into the second nonvolatile memory zone; and

neutralizing the erroneous temporary information structure by writing of erased metadata and overwriting of programmed metadata of the erroneous temporary information structure.

4. The method of claim 1, wherein the writing the data in the block of the first nonvolatile memory zone comprises:

writing a first part of the start flag;

writing the identifier of the temporary information structure and the information about the location of the block in the first nonvolatile memory zone;

writing a second part of the start flag;

writing the data in the block of the first nonvolatile memory zone; and

writing the final flag.

5. The method of claim 1 comprising:

defining erasable pages in the first nonvolatile memory zone, a page comprising several blocks; and

erasing a page of the first nonvolatile memory zone;

in conjunction with the erasing of the page of the first nonvolatile memory zone, writing in the second nonvolatile memory zone a temporary information structure associated with the erasing of the page of the first nonvolatile memory zone, wherein the temporary information structure associated with the erasing of the page of the first nonvolatile memory zone comprises;

a start flag associated with the erasing of the page of the first nonvolatile memory zone;

an identifier of the temporary information structure associated with the erasing of the page of the first nonvolatile memory zone;

an information about a location of the page of the first nonvolatile memory zone; and

a final flag associated with the erasing of the page of the first nonvolatile memory zone.

6. The method of claim 5 wherein the erasing the page of the first nonvolatile memory zone comprises:

writing a first part of the start flag associated with the erasing of the page;

writing the identifier of the temporary information structure associated with the erasing of the page of the first nonvolatile memory zone and the information about the location of the of the page of the first nonvolatile memory zone;

writing a second part of the start flag associated with the erasing of the page;

erasing the page of the first nonvolatile memory zone; and

writing the final flag associated with the erasing of the page.

7. The method of claim 1 comprising:

defining a virtual memory comprising logical pages each having a logical address;

defining, in the logical pages, logical blocks each having a logical address;

defining write commands and read commands of data in the logical blocks;

defining, in the first nonvolatile memory zone, erasable physical pages, each having a physical address;

defining, in the erasable physical pages, programmable physical blocks of a same size as the logical blocks, each programmable physical block having a physical address; and

defining, in the second nonvolatile memory zone, metadata structures associated with the physical blocks, the metadata structures associated with the physical blocks comprising information about a status of each physical block, the status of each physical block being from among the following statuses;

block erased, block containing a valid data, or block containing an invalid data.

8. The method of claim 7 comprising:

configuring metadata structures that form descriptors, including configuring metadata structures that form a descriptor being associated with a physical page in the first nonvolatile memory zone, wherein the descriptor includes;

a first field containing an address of the physical page in the first nonvolatile memory zone or a physical address index;

a second field containing a logical address of a logical page in the virtual memory or logical address index; and

for each physical block in the physical page in the first nonvolatile memory zone with which the descriptor is associated, a third field containing;

an information about a location of the physical block in the physical page;

an information about a status of the physical block, the status of the physical block in the physical page being from the at least three following statuses;

block erased, block containing a valid data, or block containing an invalid data; and

an information about a location, in the logical page in the virtual memory, of a logical block, data of which is stored in the physical block.

9. The method of claim 7, wherein the information included in the temporary information structure about the location of the block in the first nonvolatile memory zone includes information about a location in the second nonvolatile memory zone of a metadata structure associated with a block to program in the first nonvolatile memory zone.

10. The method of claim 1 comprising:

in response to a read command of other data including a logical address of the other data;

finding in the second nonvolatile memory zone a descriptor containing the logical address of the other data and associated with valid data;

reading in the descriptor containing the logical address of the other data an address of the other data in the first nonvolatile memory zone; and

reading the other data in the first memory zone.

11. The method of claim 1 comprising:

erasing a metadata page of the second nonvolatile memory zone, the metadata page containing only invalid metadata; and

in conjunction with the erasing of the metadata page, writing in the second nonvolatile memory zone, metadata associated with the erasing of the metadata page, the metadata associated with the erasing of the metadata page being written in a temporary information structure associated with the erasing of the metadata page, the temporary information structure associated with the erasing of the metadata page including;

a start flag associated with the erasing of the metadata page;

an identifier of the temporary information structure associated with the erasing of the metadata page;

an information about a location of the metadata page in the second memory zone; and

a final flag associated with the erasing of the metadata page.

12. The method of claim 11 comprising writing, in the temporary information structure associated with the erasing of the metadata page, a value of a wear counter associated with the metadata page, the wear counter representative of a number of erase cycles that the metadata page has undergone.

13. The method of claim 1 comprising:

detecting an anomaly in a temporary information structure; and

performing an action aiming to correct effects of a cause of the anomaly and to put the first nonvolatile memory zone or the second nonvolatile memory zone back into a state that the first nonvolatile memory zone or the second nonvolatile memory zone was in before the cause of the anomaly occurred.

14. The method of claim 1 comprising defining the first nonvolatile memory zone and the second nonvolatile memory zone within one nonvolatile memory.

15. An integrated circuit comprising:

a processing unit; and

at least one nonvolatile memory, communicatively coupled to the processing unit, comprising electrically erasable and programmable memory cells, wherein the processing unit is configured to receive write or read commands and to execute commands that cause the following to be performed;

writing data in a block of a first nonvolatile memory zone that is programmable by block;

in conjunction with the writing the data in the block of the first nonvolatile memory zone, writing in a second nonvolatile memory zone containing metadata associated with data in the first nonvolatile memory zone, metadata associated with the writing of the data in the block, the metadata being written in a temporary information structure associated with the writing of the data in the block, wherein the temporary information structure associated with the writing of the data in the block includes;

a start flag;

an identifier of the temporary information structure;

an information about a location of the block in the first nonvolatile memory zone; and

a final flag; and

in conjunction with a power-on of the first nonvolatile memory zone, searching for an anomaly in temporary information structures present in the second nonvolatile memory zone.

16. The integrated circuit of claim 15, wherein the processing unit is further configured to execute commands that cause detecting of an anomaly in a temporary information structure present in the second nonvolatile memory zone based on flags of the temporary information structure present in the second nonvolatile memory zone not having a same logic state, the logic state being a state of erased or written.

17. The integrated circuit of claim 15, wherein the processing unit is further configured to execute commands that cause the following to be performed:

upon a detection of an anomaly in an erroneous temporary information structure present in the second nonvolatile memory zone;

recopying the erroneous temporary information structure into the second nonvolatile memory zone; and

neutralizing the erroneous temporary information structure by writing of erased metadata and overwriting of programmed metadata of the erroneous temporary information structure.

18. The integrated circuit of claim 15, wherein the writing the data in the block of the first nonvolatile memory zone comprises:

writing a first part of the start flag;

writing the identifier of the temporary information structure and the information about the location of the block in the first nonvolatile memory zone;

writing a second part of the start flag;

writing the data in the block of the first nonvolatile memory zone; and

writing the final flag.

19. The integrated circuit of claim 15, wherein the processing unit is further configured to execute commands that cause the following to be performed:

in response to a read command of other data including a logical address of the other data;

finding in the second nonvolatile memory zone a descriptor containing the logical address of the other data and associated with valid data;

reading in the descriptor containing the logical address of the other data an address of the other data in the first nonvolatile memory zone; and

reading the other data in the first memory zone.

20. A portable device comprising:

a portable device housing; and

an integrated circuit within the housing, the integrated circuit comprising;

a processing unit; and

at least one nonvolatile memory, communicatively coupled to the processing unit, comprising electrically erasable and programmable memory cells, wherein the processing unit is configured to receive write or read commands and to execute commands that cause the following to be performed;

writing data in a block of a first nonvolatile memory zone that is programmable by block;

in conjunction with the writing the data in the block of the first nonvolatile memory zone, writing in a second nonvolatile memory zone containing metadata associated with data in the first nonvolatile memory zone, metadata associated with the writing of the data in the block, the metadata being written in a temporary information structure associated with the writing of the data in the block, wherein the temporary information structure associated with the writing of the data in the block includes;

a start flag;

an identifier of the temporary information structure;

an information about a location of the block in the first nonvolatile memory zone; and

a final flag; and

in conjunction with a power-on of the first nonvolatile memory zone, searching for an anomaly in temporary information structures present in the second nonvolatile memory zone.

21. he portable device claim 20, wherein the processing unit is further configured to execute commands that cause detecting of an anomaly in a temporary information structure present in the second nonvolatile memory zone based on flags of the temporary information structure present in the second nonvolatile memory zone not having a same logic state, the logic state being a state of erased or written.

22. The portable device of claim 20, wherein the processing unit is further configured to execute commands that cause the following to be performed:

upon a detection of an anomaly in an erroneous temporary information structure present in the second nonvolatile memory zone;

recopying the erroneous temporary information structure into the second nonvolatile memory zone; and

neutralizing the erroneous temporary information structure by writing of erased metadata and overwriting of programmed metadata of the erroneous temporary information structure.

23. The portable device of claim 20, wherein the writing the data in the block of the first nonvolatile memory zone comprises:

writing a first part of the start flag;

writing the identifier of the temporary information structure and the information about the location of the block in the first nonvolatile memory zone;

writing a second part of the start flag;

writing the data in the block of the first nonvolatile memory zone; and

writing the final flag.

24. The portable device of claim 20, wherein the processing unit is further configured to execute commands that cause the following to be performed:

in response to a read command of other data including a logical address of the other data;

finding in the second nonvolatile memory zone a descriptor containing the logical address of the other data and associated with valid data;

reading in the descriptor containing the logical address of the other data an address of the other data in the first nonvolatile memory zone; and

reading the other data in the first memory zone.