Diagnostic Data Capture in a Computing Environment

• US 20110072310A1
• Filed: 09/07/2010
• Published: 03/24/2011
• Est. Priority Date: 09/18/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lee, Phil R., Lewis, Roger G., Wright, Andy, Mitchell, Ian J., Robinson, Alan C.
• Granted Patent: US 8,489,938 B2
• Time in Patent Office: Days
• US Class Current: 714/38.1
• CPC Class Codes: G06F 11/366 using diagnostics G06F11/0703 takes precedence

Abstract

A method in a multithreaded computing environment for capturing diagnostic data, the method comprising the steps of: in response to a determination that the computing environment is in a predetermined invalid state, a first thread recording diagnostic data for the computing environment, wherein the determination includes a verification that the invalid state corresponds to a state other than a transient state of the computing environment corresponding to a transition of the computing environment by a second thread from a first valid state to a second valid state. An apparatus and computer program element for providing such diagnostic data capture are also provided.

Claims

1. A method in a multithreaded computing environment for capturing diagnostic data, the method comprising the steps of:

in response to a determination that the computing environment is in a predetermined invalid state, a first thread recording diagnostic data for the computing environment,

wherein the determination includes a verification that the invalid state corresponds to a state other than a transient state of the computing environment, the transient state corresponding to a transition of the computing environment by one or more other threads from a first valid state to a second valid state.

2. The method of claim 1, wherein the invalid state is indicated by the contents of data in a data store of the computing environment.

3. The method of claim 2, wherein the data is corrupt.

4. The method of claim 2, wherein the data is incomplete.

5. The method of claim 1, wherein the invalid state is indicated by a sequence of events taking place in the computing environment.

6. The method of claim 5, wherein the sequence of events correspond to processing actions taking place in one or more threads in the computing environment.

7. The method of claim 1, wherein the verification is based on one or more rules for identifying transient states.

8. The method of claim 7, wherein the one or more rules are based on previous behavior of the computing environment.

9. The method of claim 8, wherein the one or more rules are identified based on feedback from an operator of the computing environment indicating that a state of the computing environment is a transient state.

10. The method of claim 1, wherein the verification includes the first thread performing additional processing.

11. The method of claim 10, wherein the additional processing including the first thread repeating the determination that the computing environment is in a predetermined invalid state.

12. The method of claim 11, wherein the additional processing further includes the first thread delaying before repeating the determination.

15. A computer program element comprising computer program code stored thereon to, when loaded into a computer system and executed thereon, cause the computer to perform the steps of the method as claimed in claim 1.

13. Apparatus in a multithreaded computing environment for capturing diagnostic data, the apparatus comprising a recorder for, in response to a determination that the computing environment is in a predetermined invalid state, a first thread to record diagnostic data for the computing environment, wherein the determination includes a verification that the invalid state corresponds to a state other than a transient state of the computing environment, the transient state corresponding to a transition by at least one other thread from a first valid state to a second valid state.

14. An apparatus comprising:

a central processing unit;

a memory subsystem;

an input/output subsystem; and

a bus subsystem interconnecting the central processing unit, the memory subsystem, the input/output subsystem; and

the apparatus as claimed in claim 13.