Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design
First Claim
1. An automated method for positioning gate array circuits in an integrated circuit design, the method comprising:
- providing an initial integrated circuit design including logic cells positioned aligned on a single step size grid and gate array fill circuits positioned in a space between adjacent logic cells, wherein the size of each gate array fill circuit is a multiple of a least common multiple step size, and wherein each gate array fill circuit is aligned with a least common multiple step size grid positioned between adjacent logic cells with respect to at least one of the adjacent logic cells and aligned with the single step size grid such that each least common multiple step size grid includes the maximum number of least common multiple step size grid cells that may be positioned in the space between the adjacent logic cells;
receiving a gate array logic element design to be placed in the integrated circuit design;
automatically positioning the gate array logic element between adjacent logic cells in alignment with the least common multiple step size grid; and
automatically positioning gate array fill circuits aligned with the least common multiple step size grid between adjacent logic cells to fill the space between adjacent logic cells unoccupied by the gate array logic element.
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Abstract
An automated method and apparatus for positioning gate array circuits in an integrated circuit design. An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon. The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits. A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits.
135 Citations
20 Claims
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1. An automated method for positioning gate array circuits in an integrated circuit design, the method comprising:
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providing an initial integrated circuit design including logic cells positioned aligned on a single step size grid and gate array fill circuits positioned in a space between adjacent logic cells, wherein the size of each gate array fill circuit is a multiple of a least common multiple step size, and wherein each gate array fill circuit is aligned with a least common multiple step size grid positioned between adjacent logic cells with respect to at least one of the adjacent logic cells and aligned with the single step size grid such that each least common multiple step size grid includes the maximum number of least common multiple step size grid cells that may be positioned in the space between the adjacent logic cells; receiving a gate array logic element design to be placed in the integrated circuit design; automatically positioning the gate array logic element between adjacent logic cells in alignment with the least common multiple step size grid; and automatically positioning gate array fill circuits aligned with the least common multiple step size grid between adjacent logic cells to fill the space between adjacent logic cells unoccupied by the gate array logic element. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A computer program product including a computer readable storage medium having stored thereon computer program instructions for controlling a data processing system to automatically position gate array circuits in an integrated circuit design, comprising:
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computer program instructions stored on the computer readable storage medium to receive an initial integrated circuit design including logic cells positioned aligned on a single step size grid and gate array fill circuits positioned in a space between adjacent logic cells, wherein the size of each gate array fill circuit is a multiple of a least common multiple step size, and wherein each gate array fill circuit is aligned with a least common multiple step size grid positioned between adjacent logic cells with respect to at least one of the adjacent logic cells and aligned with the single step size grid such that each least common multiple step size grid includes the maximum number of least common multiple step size grid cells that may be positioned in the space between the adjacent logic cells; computer program instructions stored on the computer readable storage medium to receive a gate array logic element design to be placed in the integrated circuit design; computer program instructions stored on the computer readable storage medium to position automatically the gate array logic element between adjacent logic cells in alignment with the least common multiple step size grid; and computer program instructions stored on the computer readable storage medium to position automatically gate array fill circuits aligned with the least common multiple step size grid between adjacent logic cells to fill the space between adjacent logic cells unoccupied by the gate array logic element. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An apparatus for positioning gate array circuits in an integrated circuit design, comprising:
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a processor unit; and a memory coupled to the processor unit and having stored therein instructions that are readable by the processor unit for controlling the processor unit to receive an initial integrated circuit design including logic cells positioned aligned on a single step size grid and gate array fill circuits positioned in a space between adjacent logic cells, wherein the size of each gate array fill circuit is a multiple of a least common multiple step size, and wherein each gate array fill circuit is aligned with a least common multiple step size grid positioned between adjacent logic cells with respect to at least one of the adjacent logic cells and aligned with the single step size grid such that each least common multiple step size grid includes the maximum number of least common multiple step size grid cells that may be positioned in the space between the adjacent logic cells; receive a gate array logic element design to be placed in the integrated circuit design; position automatically the gate array logic element between adjacent logic cells in alignment with the least common multiple step size grid; and position automatically gate array fill circuits aligned with the least common multiple step size grid between adjacent logic cells to fill the space between adjacent logic cells unoccupied by the gate array logic element. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification