INDEXING OF ELECTRONIC DEVICES DISTRIBUTED ON DIFFERENT CHIPS

• US 20110073966A1
• Filed: 09/30/2010
• Published: 03/31/2011
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: PIVIDORI, Luca, FREGUGLIA, Alessandro
• Granted Patent: US 9,099,480 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: H01L 21/02065 the processing being a planarization of insulating layers
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An embodiment of a method is proposed for indexing electronic devices. The embodiment includes the steps of forming a plurality of first chips in a first wafer, forming a plurality of second chips in a second wafer, forming the electronic devices by coupling each first chip with a corresponding second chip, and forming an index on each electronic device; the index is indicative of a position of the corresponding first chip in the first wafer. In an embodiment, the step of forming an index includes forming a first portion of the index on the first chip, and forming a second portion of the index on the second chip.

Claims

1. A method for indexing electronic devices, the method including the steps of:

forming a plurality of first chips in a first wafer,

forming a plurality of second chips in a second wafer,

forming a plurality of electronic devices by coupling each first chip with a corresponding second chip, and

forming an index on each electronic device, the index being indicative of a position of the corresponding first chip in the first wafer,

wherein

the step of forming an index includes;

forming a first portion of the index on the first chip, and

forming a second portion of the index on the second chip.

2. The method according to claim 1, wherein the first wafer includes a plurality of equal areas each one including a subset of the first chips, the first portion of the index being indicative of a position of the first chip in the corresponding area and the second portion of the index being indicative of a position of the corresponding area in the first wafer.

3. The method according to claim 2, wherein the step of forming a plurality of first chips includes:

forming the first chips of each subset concurrently in the corresponding area, the subsets being formed in succession in the first wafer,

wherein the step of forming a plurality of second chips includes;

forming the second chips concurrently in the second wafer,

wherein the step of forming a plurality of electronic devices includes;

forming a composite wafer by joining each first chip of the first wafer to the corresponding second chip of the second wafer, and

forming each electronic device by cutting the corresponding joined first chip and second chip from the composite wafer,

wherein the step of forming a first portion of the index includes;

forming the first portions of the indexes on the first chips of each subset concurrently, the first portions of the indexes of the subsets being formed in succession in the first wafer, and

wherein the step of forming a second portion of the index includes;

 

forming the second portions of the indexes on the second chips concurrently in the second wafer.

4. The method according to claim 1, wherein each electronic device is a Micro-Electro-Mechanical device, the first chip of the electronic device including sensor means and the second chip of the electronic device including a cover for protecting the sensor means.

5. The method according to claim 1, wherein for each electronic device the second chip covers a functional area of the first chip, the first portion of the index being included in a terminal area of the first chip being not covered by the second chip.

6. The method according to claim 5, wherein the step of forming a plurality of electronic devices includes:

forming a recess and a further recess on each second chip in the second wafer,

coupling the first wafer with the second wafer, the recess and the further recess of each second chip covering the functional area and the terminal area, respectively, of the corresponding first chip, and

removing part of the second wafer until reaching the further recess of each second chip thereby uncovering the terminal area of the corresponding first chip.

7. The method according to claim 6, wherein the step of removing part of the second wafer is localised to selectively remove part of each second chip associated with the corresponding further recess.

8. The method according to claim 6, wherein each further recess is deeper than each recess, the step of removing part of the second wafer including planarizing the second wafer without reaching the recess, the step of forming a second portion of the index on the second chip being performed after said planarizing of the second wafer.

9. The method according to claim 1,

wherein the step of forming a plurality of first chips includes:

forming the first chips in groups, the first chips of each group having a different orientation in the first wafer; and

wherein the step of forming a first portion of the index includes;

forming the first portion of the index on the first chips of each group with a common value, the first portion of the index of the first chips of the group being formed with reciprocal different orientations with respect to a common reading reference of the first chips of the group.

10. The method according to claim 9, wherein the step of forming the first chips in groups, includes:

forming the first chips in pairs of two first chips, the two first chips of each pair being rotated by 180°

with respect to each other.

11. The method according to claim 9, wherein the first portion of the index includes at least one digit, the step of forming the first portion of the index on the first chips of each group including:

forming each digit of the first portion of the index on each first chip of the group overturned with respect to the corresponding digit of each other first chip of the group.

12. The method according to claim 9, wherein the common reading reference of the first chips includes a set of contacts of each first chip.

13. An electronic device including a first chip, a second chip coupled with the first chip, and an index of the first chip,

wherein the index includes a first portion on the first chip and a second portion on the second chip.

14. The electronic device according to claim 13, wherein the electronic device is a Micro-Electro-Mechanical device, the first chip including sensor means and the second chip including a cover for protecting the sensor means.

15. The electronic device according to claim 13, wherein the first portion of the index is defined by a value thereof and an orientation thereof with respect to a common reading reference of the first chips.

16. An integrated circuit, comprising:

a first die;

a second die;

a first location identifier located on the first die; and

a second location identifier located on the second die, the first and second location identifiers together indicating a wafer location from which at least one of the first and second dies originated.

17. The integrated circuit of claim 16 wherein one of the first and second dies is disposed over the other of the first and second dies.

18. The integrated circuit of claim 16 wherein the first and second dies originated from respective wafers.

19. The integrated circuit of claim 16 wherein the first and second dies originated from a same wafer.

20. The integrated circuit of claim 16 wherein:

the first location identifier indicates a wafer region from which at least one of the first and second dies originated; and

the second location identifier indicates a section of the wafer region from which the at least one of the first and second dies originated.

21. The integrated circuit of claim 16 wherein the first and second location identifiers together indicate respective wafer locations from which the first and second dies originated.

22. The integrated circuit of claim 16 wherein the first and second location identifiers together indicate respective wafer locations of different wafers from which the first and second dies originated.

23. The integrated circuit of claim 16 wherein:

one of the first and second location identifiers comprises a row indicator and a column indicator that together indicate a row and column location of a wafer region; and

the other of the first and second location identifiers comprises a number that indicates a section of the wafer region.

24. The integrated circuit of claim 16 wherein at least one of the first and second location identifiers comprises a number including at least one reverse digit.

25. The integrated circuit of claim 16 wherein:

one of the first and second dies comprises a microelectromechanical device; and

the other of the first and second dies comprises a cover for the microelectromechanical device.

26. A wafer, comprising:

a location having multiple coordinates;

at least one die disposed at the location; and

at least one, but fewer than all, of the coordinates disposed on the die.

27. The wafer of claim 26 wherein the location has two coordinates.

28. The wafer of claim 26 wherein the location has a region coordinate and a region-section coordinate.

29. The wafer of claim 26 wherein:

the location has a region coordinate and a region-section coordinate; and

only the region coordinate is disposed on the die.

30. The wafer of claim 26 wherein:

the location has a region coordinate and a region-section coordinate; and

only the region-section coordinate is disposed on the die.

31. The wafer of claim 26 wherein a row coordinate and column coordinate are disposed on the at least one die, the row and column coordinates together indicating a region of the wafer in which the location is disposed.

32. The wafer of claim 26 wherein a row coordinate and column coordinate are disposed on the at least one die, the row and column coordinates together indicating a region of the wafer in which the location is disposed, the row and column coordinates not indicating a section of the region in which the location is disposed.

33. The wafer of claim 26 wherein the at least one die comprises a microelectromechanical device.

34. The wafer of claim 26 wherein the at least one die comprises a cover for a device disposed on another die.

35. The wafer of claim 26 wherein the wafer comprises two dies that are substantially symmetrical about an axis of symmetry that separates the two dies.

36. An integrated-circuit die, comprising:

a wafer-origination location having multiple coordinates; and

at least one, but fewer than all, of the coordinates disposed on the die.

37. The integrated-circuit die of claim 36 wherein:

the wafer-origination location has a region coordinate and a region-section coordinate; and

only the region coordinate is disposed on the die.

38. The integrated-circuit die of claim 36 wherein:

the wafer-origination location has a region coordinate and a region-section coordinate; and

only the region-section coordinate is disposed on the die.

39. The integrated-circuit die of claim 36 wherein a row coordinate and column coordinate are disposed on the die, the row and column coordinates together indicating a wafer region of the wafer-origination location.

40. The integrated-circuit die of claim 36 wherein a row coordinate and column coordinate are disposed on the die, the row and column coordinates together indicating a wafer region of the wafer-origination location, the row and column coordinates not indicating a section of the wafer region.

41. The integrated-circuit die of claim 36, further comprising a microelectromechanical device.

42. The integrated-circuit die of claim 36, further comprising a cover.

43. A system, comprising:

a first integrated circuit, comprising;

a first die;

a second die;

a first location identifier located on the first die; and

a second location identifier located on the second die, the first and second location identifiers together indicating a wafer location from which at least one of the first and second dies originated; and

a second integrated circuit coupled to the first integrated circuit.

44. The system of claim 43 wherein the second integrated circuit is disposed on at least one of the first and second dies.

45. The system of claim 43 wherein the second integrated circuit is disposed on a third die.

46. The system of claim 43 wherein the first integrated circuit comprises a microelectromechanical device.

47. The system of claim 43 wherein:

the first die comprises a microelectromechanical device; and

the second die comprises a cover disposed over the first die.

48. The system of claim 43 wherein the second integrated circuit comprises a controller.

49. A method, comprising:

forming on a first die at a location of a first wafer, the location having multiple location components that together define the location; and

disposing on the die at least one, but not all, of the location components.

50. The method of claim 49 wherein disposing comprises disposing on the die a location component that indicates a multi-die region of the wafer, the die being disposed in the multi-die region.

51. The method of claim 49 wherein disposing comprises disposing on the die a location component that indicates a single-die section of a multi-die region of the wafer, the die being disposed in the single-die section.

52. The method of claim 49, further comprising:

forming a second die at a same location of a second wafer; and

disposing on the second die the one or more location components not disposed on the first die.

53. The method of claim 52, further comprising coupling the first wafer to the second wafer such that one of the first and second dies is disposed over the other of the first and second dies.

54. A method, comprising:

aligning a first wafer with a second wafer; and

coupling the first wafer to the second wafer such that a first die of the first wafer is disposed over a second die of the second wafer, the first die disposed at a first location of the first wafer, the first location having multiple location components that together define the location, some of the location components being indicated on the first die, the other of the location components being indicated on the second die.

55. The method of claim 54 wherein the second die is disposed at a second location of the second wafer, the second location having the same location components as the first location.