END OF LIFE DETECTION FOR A BATTERY

• US 20110074434A1
• Filed: 09/30/2009
• Published: 03/31/2011
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Staton, Kenneth L.
• Granted Patent: US 8,410,783 B2
• Time in Patent Office: Days
• US Class Current: 324/433
• CPC Class Codes: G01R 31/386 using test-loads
• CPC Class Codes: G01R 31/392 Determining battery ageing or deterioration, e.g. state of health

Abstract

One particular implementation conforming to aspects of the present invention takes the form of a method for detecting the end of life of a battery for an electronic device. The method may include calculating the voltage of the battery in an unloaded state, holding the sampled unloaded battery voltage, measuring a loaded battery voltage, calculating the difference between the unloaded and loaded battery voltages and amplifying the calculated difference. Other implementations may take the form of a circuit to perform one or more of the operations of the above method. The circuit may include a sample and hold section and a differential amplifier to provide the amplified difference to a microcontroller for analysis. The microcontroller may also provide a warning or indication to the device or to a user of the device when the battery nears the end of life.

Claims

1. A circuit for detecting the end of life of a battery of an electronic device comprising:

a first node electrically connected to a battery;

a load intermittently electrically connected to the first node, the load configured to be applied and removed from the circuit;

a sample and hold circuit electrically connected to the first node, the sample and hold circuit configured to sample and hold an unloaded battery voltage; and

a differential amplifier electrically connected to the sample and hold circuit, the differential amplifier configured to calculate and amplify a difference between the sampled unloaded battery voltage and a loaded battery voltage.

2. The circuit of claim 1 further comprising:

an analog to digital converter electrically connected to an output of the differential amplifier, the analog to digital converter configured to digitize the amplified difference between the sampled unloaded battery voltage and the loaded battery voltage; and

a microcontroller configured to compare the digitized amplified difference with a predetermined threshold value.

3. The circuit of claim 1 wherein the sample and hold circuit comprises:

a capacitor electrically connected between a second node and ground;

a first operational amplifier comprising an inverting input, a non-inverting input and an output, wherein the non-inverting input is electrically connected to the second node and the output is electrically connected to the inverting input; and

a field effect transistor comprising a base terminal, a drain terminal, a gate terminal and a source terminal, wherein the base terminal and the source terminal are electrically connected to the first node and the drain terminal is electrically connected to the second node.

4. The circuit of claim 3 further comprising:

an enable input pin electrically connected to the gate terminal of the field effect transistor, wherein an enable signal is input on the enable input pin to control the flow of current through the field effect transistor and thereby control the charging of the capacitor.

5. The circuit of claim 4 wherein the enable signal and the load are controlled by a microcontroller.

6. The circuit of claim 3 wherein the differential amplifier comprises:

a first resistor electrically connected between an output of the first operational amplifier and a non-inverting input of a second operational amplifier;

a second resistor electrically connected to the non-inverting input of the second operational amplifier;

a third resistor electrically connected between the first node and an inverting input of the second operational amplifier; and

a fourth resistor electrically connected between an output of the second operational amplifier and the inverting input of the second operational amplifier.

7. The circuit of claim 1 wherein the sample and hold circuit comprises:

a reference voltage input, the reference voltage input approximating the unloaded battery voltage;

a capacitor electrically connected to the reference voltage input; and

a first operational amplifier electrically connected to the capacitor.

8. The circuit of claim 1 wherein the sample and hold circuit comprises:

a first diode comprising an anode end and a cathode end, the anode end of the first diode electrically connected to the first node and the cathode end electrically connected to a second node;

a capacitor electrically connected to the second node; and

a first operational amplifier comprising an inverting input, a non-inverting input and an output, wherein the non-inverting input is electrically connected to the second node and the output is electrically connected to the inverting input.

9. The circuit of claim 8 further comprising:

a second diode comprising an anode end and a cathode end, the anode end of the second diode electrically connected to the first node; and

a third operational amplifier comprising an inverting input, a non-inverting input and an output, wherein the cathode end of the second diode is electrically connected to the non-inverting input and the output of the third operational amplifier is electrically connected to the inverting input.

10. The circuit of claim 9 wherein the differential amplifier comprises:

a first resistor electrically connected between an output of the first operational amplifier and a non-inverting input of a second operational amplifier;

a second resistor electrically connected to the non-inverting input of the second operational amplifier;

a third resistor electrically connected between the output of the third operational amplifier and an inverting input of the second operational amplifier; and

a fourth resistor electrically connected between an output of the second operational amplifier and the inverting input of the second operational amplifier.

11. The circuit of claim 1 wherein the sample and hold circuit comprises an active peak detection circuit.

12. The circuit of claim 11 wherein the active peak detection circuit comprises:

a first operational amplifier comprising an inverting input, a non-inverting input and an output, the non-inverting input electrically connected to the first node;

a first diode comprising an anode end and a cathode end, the anode end of the first diode electrically connected to the output of the first operational amplifier and the cathode end of the first diode electrically connected to a second node;

a second diode comprising an anode end and a cathode end, the anode end of the second diode electrically connected to the second node and the cathode end of the second diode electrically connected to a third node;

a second operational amplifier comprising an inverting input, a non-inverting input and an output, the non-inverting input electrically connected to the third node and the output fed back to the inverting input of the second operational amplifier;

a capacitor electrically connected to the third node; and

a first resistor electrically connected between the inverting input of the second operational amplifier and the second node;

wherein the inverting input to the first operational amplifier is electrically connected to the third node.

13. The circuit of claim 12 wherein the differential amplifier comprises:

a second resistor electrically connected between an output of the second operational amplifier and a non-inverting input of a third operational amplifier;

a third resistor electrically connected to the non-inverting input of the third operational amplifier;

a fourth resistor electrically connected between the first node and an inverting input of the third operational amplifier; and

a fifth resistor electrically connected between an output of the third operational amplifier and the inverting input of the third operational amplifier.

14. A method for detecting the end of the life of a battery of an electronic device comprising:

sampling a voltage of a battery while the battery is unloaded;

storing the sampled unloaded battery voltage;

measuring a voltage of the battery while a load is applied to the battery;

calculating a difference between the sampled unloaded battery voltage and the measured loaded battery voltage;

amplifying the calculated difference using a differential amplifier circuit; and

comparing the amplified difference to a predetermined value to detect the end of the life of the battery.

15. The method of claim 14 wherein the storing operation comprises:

holding the sampled voltage in a sample and hold circuit.

16. The method of claim 14 wherein the storing operation comprises:

maintaining the sampled voltage in a computer-readable storage medium.

17. The method of claim 14 further comprising:

digitizing the amplified difference with a analog to digital converter prior to comparing the amplified difference to the predetermined value.

18. A system for detecting the end of the life of a battery of an electronic device comprising:

a sample and hold circuit configured to sample the unloaded voltage of a battery;

a differential amplifier circuit configured to receive the sampled unloaded battery voltage from the sample and hold circuit and calculate and amplify a difference between the sampled unloaded battery voltage and a loaded battery voltage; and

a microcontroller configured to receive the amplified difference from the differential amplifier and compare the amplified difference with a predetermined threshold value.

19. The system of claim 18 further comprising:

an analog to digital converter configured to receive the amplified calculated difference and digitize the received difference.

20. The system of claim 19 wherein the microcontroller is further configured to provide an enable signal to activate the sample and hold circuit and apply a load to battery.