SYMMETRICALLY OPERATING SINGLE-ENDED INPUT BUFFER DEVICES AND METHODS

• US 20110074510A1
• Filed: 12/03/2010
• Published: 03/31/2011
• Est. Priority Date: 12/18/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Amirabadi, Yadollah Eslami
• Granted Patent: US 8,036,058 B2
• Time in Patent Office: Days
• US Class Current: 330/253
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03F 2203/45091 Two complementary type differential amplifiers are paralleled, e.g. one of the p-type and one of the n-type
• CPC Class Codes: H03F 2203/45296 the AAC comprising one or more discrete capacitive elements, e.g. a transistor coupled as capacitor
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance

Abstract

Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The aforementioned input buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor that charges and discharges the drain of the second transistor responsive to the input signal transitioning to mimic the second input node transitioning in the direction opposite to the transition of the input signal, while the reference signal at the second input node is maintained at a constant voltage level.

Claims

1. A differential amplifier comprising:

a first voltage supply node and a second voltage supply node;

a first transistor coupled between the first and second voltage supply nodes, the first transistor having an input node configured to receive an input signal; and

a second transistor coupled between the first and second voltage supply nodes, the second transistor having a first terminal and a second input node configured to receive a reference signal, the first input node of the first transistor being capacitively coupled to the first terminal of the second transistor to charge and discharge the first terminal of the second transistor responsive to the input signal transitioning.

2. The differential amplifier of claim 1 wherein the first terminal is charged and discharged in a manner that mimics the reference signal at the second input node transitioning in a direction opposite the direction of a transition of the input signal.

3. The differential amplifier of claim 2 further comprising an output node coupled to a first terminal of the first transistor, wherein a logic state “

0”

is generated at the output node when the magnitude of the input signal is greater than the magnitude of the reference signal and a logic state “

1”

is generated when the magnitude of the input signal is less than the magnitude of the reference signal.

4. The differential amplifier of claim 3 wherein the first terminal of the first transistor and the first terminal of the second transistor each respectively comprises a drain terminal.

5. The differential amplifier of claim 1 wherein the first and second transistors comprise NMOS transistors having drains respectively coupled to drains of first and second PMOS transistors, wherein the gates of the PMOS transistors are coupled to each other and to the drain of the second transistor.

6. The differential amplifier of claim 1 wherein the first and second transistors comprise PMOS transistors having drains respectively coupled to drains of first and second NMOS transistors, wherein the gates of the NMOS transistors are coupled to each other and to the drain of the second transistor.

7. A method of generating an output signal by a differential amplifier, comprising:

receiving a first input signal that transitions;

receiving a second input signal, the second input signal being a reference voltage having a relatively constant magnitude; and

capacitively coupling a portion of the first input signal to a node of the differential amplifier that would transition in the same direction as a transition of the input signal responsive to a transition of the second input signal in a direction opposite the direction that the first input signal transitions.

8. The method of claim 7 wherein the differential amplifier comprises a first differential amplifier receiving the first input signal and a second differential amplifier receiving the second input signal.

9. The method of claim 8 further comprising generating an output signal having a logic state “

0”

when the magnitude of the first input signal is greater than the magnitude of the second input signal and generating the output signal having a logic state “

1”

when the magnitude of the first input signal is less than the magnitude of the second input signal.

10. A differential amplifier comprising:

an output node;

a first transistor having a first terminal configured to receive a first input signal; and

a second transistor having a second terminal capacitively coupled to the first terminal of the first transistor to provide a portion of the first input signal to the second transistor in a manner such that the drive strength of the differential amplifier is adjusted as an output signal is generated at the output node.

11. The differential amplifier of claim 10 wherein the differential amplifier is configured so that the drive strength of the differential amplifier is adjusted in a manner that mimics a second input signal received at a third terminal of the second transistor that transitions in the opposite direction relative to the first input signal transitioning at the first terminal.

12. The differential amplifier of claim 11 wherein the first terminal comprises a gate terminal of the first transistor, the second terminal comprises a drain terminal of the second transistor and the third terminal comprises a gate terminal of the second transistor.

13. The differential amplifier of claim 10 wherein the differential amplifier is configured so that the second input signal maintains a constant voltage level.

14. The differential amplifier of claim 10 wherein the differential amplifier is configured so that the differential amplifier outputs a logic state “

1”

at the output node when the magnitude of the first input signal is less than the magnitude of the second input signal, and the differential amplifier outputs a logic state “

0”

at the output node when the magnitude of the first input signal is greater than the magnitude of the second input signal.

15. The differential amplifier of claim 10, further comprising a plurality of inverters coupled in series and configured to incrementally condition the output signal.

16. A differential amplifier comprising:

a first amplifier circuit having an output node, the first amplifier circuit coupled to receive a first input signal, the first amplifier circuit configured to generate an output signal in response to the first input signal transitioning, the first amplifier circuit being capacitively coupled to receive a portion of the first input signal relative to the transition of the first input signal in a manner such that the rate at which the first amplifier circuit generates the output signal increases as the first input signal transitions; and

a second amplifier circuit being coupled in parallel to the first amplifier circuit and coupled to the output node, the second amplifier circuit being configured complementary respective to the first amplifier circuit and further coupled to receive the first input signal, the second amplifier circuit configured to generate the output signal in response to the first input signal transitioning, the second amplifier circuit being capacitively coupled to receive a portion of the first input signal relative to the transitioning of the first input signal in a manner such that the rate at which the second amplifier circuit generates the output signal increases as the first input signal transitions.

17. The differential amplifier of claim 16 wherein the first amplifier circuit comprises a first input transistor coupled to receive the first input signal and a second input transistor coupled to receive a second input signal, and wherein second amplifier circuit comprises a third input transistor coupled to receive the first input signal and a fourth input transistor coupled to receive the second input signal.

18. The differential amplifier of claim 16 wherein the first amplifier circuit is configured to drive the output node towards a first specific voltage as the input signal transitions and the second amplifier circuit is configured to drive the output node towards a second specific voltage as the input signal transitions.

19. The differential amplifier of claim 16, further comprising a plurality of inverters coupled in series and having an input of a first of the inverters coupled to the output node, the inverters being configured to condition the output signal.

20. A differential amplifier, comprising:

a first amplifier having first and second differential transistors of a first type, the first differential transistor having a gate coupled to an input voltage node, and the second differential transistor having a gate coupled to a reference voltage node, one of the first and second differential transistors having a drain coupled to an output voltage node; and

a second amplifier having third and fourth differential transistors of a second type that is different from the first type, the third differential transistor having a gate coupled to the input voltage node, and the fourth differential transistor having a gate coupled to the reference voltage node, one of the third and fourth differential transistors having a drain coupled to the output voltage node.

21. The differential amplifier of claim 20 wherein the first and second differential transistors of a first type comprise n-channel transistors, and the third and fourth differential transistors of a second type comprise p-channel transistors.

22. The differential amplifier of claim 20, further comprising:

first and second current mirror transistors of the second type coupled in series with the first and second differential transistors, respectively; and

third and fourth current mirror transistors of the first type coupled in series with the third and fourth differential transistors, respectively.

23. The differential amplifier of claim 22, further comprising:

a first capacitor coupled between the input voltage node and respective gates of the first and second current mirror transistors; and

a second capacitor coupled between the input voltage node and respective gates of the third and fourth current mirror transistors.

24. The differential amplifier of claim 22, further comprising:

a fifth transistor of the first type coupled in series with one of the first and second transistors, the fifth transistor of the first type having a gate coupled to gates of the first and second current mirror transistors; and

a fifth transistor of the second type coupled in series with one of the third and fourth transistors, the fifth transistor of the second type having a gate coupled to gates of the third and fourth current mirror transistors.