METHOD FOR EXTENDING DURATION OF A DISPLAY APPARATUS HAVING BRIGHTNESS COMPENSATION AND APPARATUS REALIZING THE SAME

• US 20110074806A1
• Filed: 12/16/2009
• Published: 03/31/2011
• Est. Priority Date: 09/25/2009
• Status: Active Grant

• Current Assignee: Holtek Semiconductor Incorporated
• Original Assignee: Holtek Semiconductor Incorporated
• Inventors: Chen, Tzong-Kwei, Shen, Chun-Lin, Liu, Yi-Chen, Kuan, Chen-Ting
• Granted Patent: US 8,379,041 B2
• Time in Patent Office: Days
• US Class Current: 345/589
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2320/0626 for control of overall brightness
• CPC Class Codes: G09G 2360/16 Calculation or use of calculated indices related to luminance levels in display data
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Abstract

For improving the drawback of brightness decay of a display due to aging, a memory can be used to store the usage time of each pixel of the display, then based upon the usage time the brightness decay of each pixel of the display can be compensated and accordingly the value for the compensation can be stored in a volatile memory and a non-volatile memory. However, the usage of the non-volatile memory is limited. Hence, the present invention discloses a new approach for storing the data so as to decrease write-in sequence per unit area for the non-volatile memory rather than increasing its storing capacity proportionally.

Claims

1. A method for extending duration of a display apparatus having brightness compensation, comprising steps of:

(a) providing a volatile memory for storing an m-bit accumulation value for the brightness compensation and an n-bit non-volatile memory;

(b) selecting a p bit value as a virtual bit value;

(c) dividing the n-bit non-volatile memory into a h-bit high-bit memory and k2 low-bit memories, wherein each of the k2 memories is long as j+p bits;

(d) moving a part of the accumulation value for brightness compensation into the h-bit high-bit memory, where the part refers to data between MSB (m^th bit of the accumulation value) and (m−

h+1)^th bit; and

(e) writing j-bit data (between (m−

h)^th bit˜

(m−

(h+j)+1)^th bit) of accumulation value for brightness compensation and the p-bit virtual bit into first one of the k2 low-bit memories, wherein, m, n, j, p, h, and k2 are integers greater than zero.

2. The method as recited in claim 1, further comprising a step of:

(f) whenever there is a change for the (m−

(h+j)+1)^th bit of the high-bit memory, sequentially writing (m−

h)^th˜

(m−

(h+j)+1)^th data of the m-bit brightness accumulation and the p-bit virtual bit into second ˜

k2^th ones of the k2 low-bit memories.

3. The method as recited in claim 2, further comprising a step of:

(g) after step (f), if there is again a change for the (m−

(h+j)+1)^th bit of the accumulation value, summing a LSB data stored in the h-bit high-bit memory and the virtual bit p and writing the result thereof to the h-bit high-bit memory and then go back to step (e).

4. The method as recited in claim 3, further comprising a step of:

(f) reading out data stored in the non-volatile memory by assembling the h-bit high-bit memory and the latest data stored in the low-bit memory.

5. The method as recited in claim 1, wherein the virtual bit value is found in the volatile memory.

6. The method as recited in claim 1, wherein the volatile memory is selected from the group consisting of a DRAM or a SRAM.

7. The method as recited in claim 1, wherein the non-volatile memory is flash memory.

8. A method for extending duration of a display apparatus having brightness compensation, comprising steps of:

(a) providing a volatile memory for storing an m-bit accumulation value for the brightness compensation and an n-bit non-volatile memory;

(b) selecting a p bit value as a virtual bit value;

(c) dividing the n-bit non-volatile memory into a (h+j)-bit complete area and k1 low-bit memories, wherein each of the k1 memories is long as j+p bits;

(d) moving a part of the accumulation value for brightness compensation into the (h+j)-bit complete area, where the part refers to data between MSB (m^th bit of the accumulation value) and (m−

(h+j)+1)^th bit; and

(e) writing j-bit data (between (m−

h)^th bit˜

(m−

(h+j)+1)^th bit) of partial accumulation value for brightness compensation and the p-bit virtual bit into first one of the k1 low-bit memories, wherein, m, n, j, p, h, and k1 are integers greater than zero.

9. The method as recited in claim 8, further comprising a step of:

(f) whenever there is a change for the (m−

(h+j)+1)^th bit of the accumulation value, sequentially writing (m−

h)^th˜

(m−

(h+j)+1)^th data of the m-bit brightness accumulation and the p-bit virtual bit into second ˜

k1^th ones of the k1 low-bit memories.

10. The method as recited in claim 9, further comprising a step of:

(g) after (f), if there is again a change for the (m−

(h+j)+1)^th bit of the accumulation value, summing a h^th-bit data stored in the (h+j)-bit complete area and the virtual bit p, and writing its result thereof to the (h+j)-bit complete area and then go back to (e).

11. The method as recited in claim 8, wherein the virtual bit value is found in the volatile memory.

12. The method as recited in claim 8, wherein the volatile memory is selected from the group consisting of a DRAM or a SRAM.

13. The method as recited in claim 8, wherein the non-volatile memory is a flash memory.

14. A long-duration display apparatus having brightness compensation, comprising:

a volatile memory, for storing a brightness accumulation for each pixel in view of different color on the display apparatus;

a non-volatile memory, for preventing the brightness accumulating from missing during its shutting down period; and

a calculating means, for accumulating the brightness of each pixel;

wherein, a write-in area of the non-volatile memory is divided into a first area and a plurality of second areas, and the first area has a bigger capacity than the second areas do.

15. The apparatus as recited in claim 14, wherein said volatile memory is selected from the group consisting of a DRAM and a SRAM.

16. The apparatus as recited in claim 14, wherein said non-volatile memory is a flash memory.

17. The apparatus as recited in claim 14, wherein said first area is used for storing complete data of the brightness accumulation or high-bit data of the brightness accumulation.

18. The apparatus as recited in claim 14, wherein said second area is used for storing low-bit data of the brightness accumulation.

19. The apparatus as recited in claim 14, wherein the calculating means is accumulating the brightness accumulation by a two-section style according to a high-bit and low-bit part of the brightness accumulation.

20. The apparatus as recited in claim 14, wherein a low-bit of the brightness accumulation and its highest carry are respectively being stored in the second area of the non-volatile memory by the calculating means, after a plurality of times, then highest carry is then being stored into a first area of the non-volatile memory.

21. The apparatus as recited in claim 14, wherein the calculating means further comprises a first adder.

22. The apparatus as recited in claim 21, wherein the calculating means further comprises a second adder.

23. The apparatus as recited in claim 22, wherein the calculating means further comprises a register.