Power Semiconductor Module and Method for Operating a Power Semiconductor Module

• US 20110075451A1
• Filed: 09/30/2010
• Published: 03/31/2011
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Stolze, Thilo, Bayerer, Reinhold
• Granted Patent: US 8,593,817 B2
• Time in Patent Office: Days
• US Class Current: 363/37
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48139 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/48724 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48747 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48824 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48847 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/78 : Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/8381 : involving forming an intermetallic compound at the bonding interface
• CPC Class Codes: H01L 2224/83825 : Solid-liquid interdiffusion
• CPC Class Codes: H01L 2224/8384 : Sintering
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/85205 : Ultrasonic bonding
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10272 : Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13033 : TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/203 : Ultrasonic frequency ranges, i.e. KHz
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: Y10T 428/24752 : Laterally noncoextensive components

Abstract

A power semiconductor module is provided in which power semiconductor chips with an aluminum-based chip metallization and power semiconductor chips with a copper-based chip metallization are included in the same module, and operated at different barrier-layer temperatures during use.

Claims

1. A power semiconductor module for use in a converter, which has a rectifier circuit and an inverter circuit, comprising:

a housing;

a first power semiconductor chip, which is a component part of the rectifier circuit and has a first semiconductor body with an upper chip metallization and a lower chip metallization;

a second power semiconductor chip, which is a component part of the inverter circuit and has a second semiconductor body with an upper chip metallization and a lower chip metallization; and

at least one ceramic substrate;

wherein the first power semiconductor chip and the second power semiconductor chip are arranged in the housing;

the upper chip metallization and/or the lower chip metallization of the first power semiconductor chip is respectively adjoined directly by one of the following first connecting means;

a fusion soldering layer or an aluminum-based bonding wire with an aluminum fraction of at least 99% by weight aluminum;

the upper chip metallization and/or the lower chip metallization of the second power semiconductor chip is respectively adjoined directly by one of the following second connecting means;

a diffusion soldering layer;

a silver-containing sintering layer;

an adhesive bonding layer or a copper-based bonding wire with a copper fraction of at least 99% by weight copper.

2. The power semiconductor module as claimed in claim 1, wherein the lower metallization of the first power semiconductor chip has at least a first sub-layer with a thickness of more than 1 μ

m or more than 2 μ

m and contains more than 99% by weight of aluminum.

3. The power semiconductor module as claimed in claim 1, wherein the lower metallization of the first power semiconductor chip is connected to an upper metallization of a ceramic substrate by means of a fusion soldering layer.

4. The power semiconductor module as claimed in claim 1, wherein the lower metallization of the second power semiconductor chip has at least one first sub-layer with a thickness of more than 1 μ

m or more than 2 μ

m and contains more than 99% by weight of copper.

5. The power semiconductor module as claimed in claim 1, wherein the lower metallization of the second power semiconductor chip is connected to an upper metallization of a ceramic substrate by means of a diffusion soldering layer, an adhesive bonding layer or by means of a silver-containing sintering layer.

6. The power semiconductor module as claimed in claim 1, wherein the upper metallization of the first power semiconductor chip has at least one first sub-layer with a thickness of more than 1 μ

m or more than 2 μ

m and contains more than 99% by weight of aluminum.

7. The power semiconductor module as claimed in claim 6, wherein a bonding wire, which contains more than 99.9% by weight of aluminum, is bonded onto the upper metallization of the first power semiconductor chip.

8. The power semiconductor module as claimed in claim 7, wherein the bonding wire directly contacts the first sub-layer of the upper metallization of the first power semiconductor chip.

9. The power semiconductor module as claimed in claim 1, wherein the upper metallization of the second power semiconductor chip has at least one first sub-layer with a thickness of more than 1 μ

m or more than 2 μ

m and contains more than 99% by weight of copper.

10. The power semiconductor module as claimed in claim 9, wherein a bonding wire, which contains more than 99.9% by weight of copper, is bonded onto the upper metallization of the second power semiconductor chip.

11. The power semiconductor module as claimed in claim 9, wherein the bonding wire directly contacts the first sub-layer of the upper metallization of the second power semiconductor chip.

12. The power semiconductor module as claimed in claim 1, wherein each ceramic substrate of the at least one ceramic substrate on which at least one power semiconductor chip is arranged has on its side facing away from its upper metallization a lower metallization which forms the underside of the power semiconductor module, and wherein, in the case of a number of ceramic substrates, the lower metallizations of the ceramic substrates are spaced apart from one another.

13. The power semiconductor module as claimed in claim 1, further comprising a metallic base plate having an upper side and an underside, wherein the underside of the base plate forms at least part of the underside of the power semiconductor module, and wherein the lower metallization of each ceramic substrate of the at least one ceramic substrate on which at least one power semiconductor chip is arranged is firmly connected to the upper side of the base plate.

14. The power semiconductor module as claimed in claim 13, wherein the first power semiconductor chip is arranged on a first ceramic substrate of the at least one ceramic substrate, and wherein the first ceramic substrate is firmly connected at its lower metallization to the upper side of the base plate by means of a fusion soldering layer.

15. The power semiconductor module as claimed in claim 14, wherein the lower metallization of the first power semiconductor chip is firmly connected to the upper metallization of the first ceramic substrate by means of a fusion soldering layer.

16. The power semiconductor module as claimed in claim 15, wherein the second power semiconductor chip is arranged on a second ceramic substrate of the at least one ceramic substrate, and wherein the second ceramic substrate is firmly connected at its lower metallization to the upper side of the base plate by means of a diffusion soldering layer, an adhesive bonding layer or by means of a silver-containing sintering layer.

17. The power semiconductor module as claimed in claim 16, wherein the lower metallization of the second power semiconductor chip is firmly connected to the upper metallization of the second ceramic substrate by means of a diffusion soldering layer, an adhesive bonding layer or by means of a silver-containing sintering layer.

18. The power semiconductor module as claimed in claim 17, wherein the base plate has at least one first segment and a second segment, and wherein:

a first ceramic substrate, on which the first power semiconductor chip is arranged, is arranged on the first segment; and

a second ceramic substrate, on which the second power semiconductor chip is arranged, is arranged on the second segment.

19. The power semiconductor module as claimed in claim 18, wherein the first segment and the second segment are formed in one piece and are connected to one another by means of one or more connecting webs.

20. The power semiconductor module as claimed in claim 18, wherein the first segment and the second segment are spaced apart from one another.

21. The power semiconductor module as claimed in claim 1, wherein all of the power semiconductor chips of the rectifier circuit are arranged on a first common ceramic substrate and are connected with their lower chip metallizations to an upper metallization of the first common ceramic substrate in each case by means of a fusion soldering layer.

22. The power semiconductor module as claimed in claim 21, wherein all of the power semiconductor chips of the inverter circuit are arranged on a second common ceramic substrate and are connected with their lower chip metallizations to an upper metallization of the second common ceramic substrate in each case by means of a diffusion soldering layer, an adhesive bonding layer or by means of a silver-containing sintering layer.

23. The power semiconductor module as claimed in claim 22, further comprising a third common ceramic substrate with an upper metallization, wherein:

the lower metallization of the first power semiconductor chip is connected to the upper metallization of the third common ceramic substrate by means of a fusion soldering layer; and

the lower metallization of the second power semiconductor chip is connected to the upper metallization of the third common ceramic substrate by means of a silver-containing sintering layer, an adhesive bonding layer or by means of a diffusion soldering layer.

24. The power semiconductor module as claimed in claim 1, wherein all of the power semiconductor chips of the rectifier circuit that are arranged in the housing have an upper chip metallization and a lower chip metallization with an aluminum fraction of in each case more than 50% by weight, and wherein all of the power semiconductor chips of the inverter circuit that are arranged in the housing have an upper chip metallization and a lower chip metallization with a copper fraction of in each case more than 50% by weight.

25. The power semiconductor module as claimed in claim 24, wherein all of the power semiconductor chips of the rectifier circuit are spatially arranged in a first group and all of the power semiconductor chips of the inverter circuit are spatially arranged in a second group on a common ceramic substrate, and wherein a smallest distance between a power semiconductor chip of the first group and a power semiconductor chip of the second group is greater than 5 mm or greater than 10 mm.

26. A method for operating a power semiconductor module, comprising:

providing a power semiconductor module having a rectifier circuit and an inverter circuit, the power semiconductor module comprising;

a housing;

a first power semiconductor chip, which is a component part of the rectifier circuit and has a first semiconductor body with an upper chip metallization and a lower chip metallization;

a second power semiconductor chip, which is a component part of the inverter circuit and has a second semiconductor body with an upper chip metallization and a lower chip metallization; and

at least one ceramic substrate;

wherein the first power semiconductor chip and the second power semiconductor chip are arranged in the housing;

the upper chip metallization and/or the lower chip metallization of the first power semiconductor chip is respectively adjoined directly by one of the following first connecting means;

a fusion soldering layer or an aluminum-based bonding wire with an aluminum fraction of at least 99% by weight aluminum;

the upper chip metallization and/or the lower chip metallization of the second power semiconductor chip is respectively adjoined directly by one of the following second connecting means;

a diffusion soldering layer;

a silver-containing sintering layer;

an adhesive bonding layer or a copper-based bonding wire with a copper fraction of at least 99% by weight copper;

operating the first power semiconductor chip at a barrier-layer temperature of less than 150°

C. or less than 125°

C.; and

operating the second power semiconductor chip at a barrier-layer temperature of more than 150°

C.

27. The method as claimed in claim 26, comprising:

operating all of the power semiconductor chips of the rectifier circuit arranged in the housing at a barrier-layer temperature of less than 150°

C. or less than 125°

C.; and

operating all of the power semiconductor chips of the inverter circuit arranged in the housing at a barrier-layer temperature of more than 150°

C.