CIRCUIT AND METHOD FOR GENERATING REFERENCE VOLTAGE, PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS AND READ METHOD USING THE SAME

• US 20110075473A1
• Filed: 12/29/2009
• Published: 03/31/2011
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KIM, Soo Gil, LEE, Se Ho, PARK, Hae Chan
• Granted Patent: US 8,159,869 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A circuit for generating a reference voltage includes at least one reference cell, a reference cell write driver, a reference cell sense amplifier, and a voltage compensation unit. The reference cell is a variable resistance memory cell. The reference cell write driver writes data to the reference cell. The reference cell sense amplifier reads out the data stored in the reference cell on the basis of a predetermined reference voltage. A voltage compensation unit outputs a compensation reference voltage by controlling the reference voltage in accordance with the output value of the sense amplifier.

Claims

1. A circuit for generating reference voltage, comprising:

at least one reference cell, the reference cell being a variable resistance memory cell;

a reference cell write driver configured to write data to the reference cell;

a reference cell sense amplifier configured to output an output value by reading out the data stored in the reference cell on the basis of a predetermined reference voltage; and

a voltage compensation unit configured to output a compensation reference voltage having a value adjusted according to the output value of the reference cell sense amplifier.

2. The circuit for generating reference voltage according to claim 1, wherein the voltage compensation unit is configured to increase or decrease the reference voltage according to the difference between the voltage level of the data stored in the reference cell and the voltage level of the reference voltage in order to output the increased or decreased reference voltage as the compensation reference voltage.

3. The circuit for generating reference voltage according to claim 2, wherein the reference cell is a multi-level memory cell and the reference voltage is a reference voltage for discriminating the most significant bit.

4. The circuit for generating reference voltage according to claim 1, further comprising at least one memory cell corresponding to the at least one reference cell, and a memory cell sense amplifier,

wherein the reference cell write driver is configured to write data to the reference cell in response to a write enable signal indicating a write is to be performed in the corresponding memory cell,

wherein the memory cell sense amplifier is configured to read data stored in the memory cell using the compensation reference voltage.

5. A method of generating reference voltage, comprising:

writing data to a reference cell, the reference cell being a variable resistance memory cell;

reading the data of the reference cell in accordance with a predetermined reference voltage; and

generating a compensation reference voltage by adjusting the reference voltage in accordance with the result of reading the data of the reference cell.

6. The method of generating reference voltage according to claim 5, wherein the step of reading the data of the reference cell includes detecting the difference of voltage level between the voltage level of the reference voltage and the voltage level of the data stored in the reference cell.

7. The method of generating reference voltage according to claim 6, wherein the step of generating the compensation reference voltage includes increasing or decreasing the reference voltage according to the difference of voltage level.

8. A phase change random access memory (PCRAM) apparatus, comprising:

a memory cell array including at least one memory cell coupled between a word line and a bit line;

a reference voltage generating circuit comprising at least one reference cell and configured to generate a compensation reference voltage by writing data to a reference cell, reading the data from the reference cell, and adjusting a predetermined reference voltage; and

a sense amplifier configured to read data of the memory cell in accordance with the compensation reference voltage.

9. The phase change random access memory apparatus according to claim 8, wherein the reference voltage generating circuit comprises:

the at least one reference cell coupled between the word line and a reference cell bit line;

a reference cell write driver configured to write data to the reference cell;

a reference cell sense amplifier configured to output an output value by reading out the data stored in the reference cell on the basis of the reference voltage; and

a voltage compensation unit configured to output the compensation reference voltage by adjusting the reference voltage in accordance with the output value of the sense amplifier.

10. The phase change random access memory apparatus according to claim 9, wherein the bit line connected to the memory cell array is enabled after the reference cell bit line is enabled and data is written, in a write operation of the phase change random access memory apparatus.

11. The phase change random access memory apparatus according to claim 10, wherein the bit line connected to the memory cell array is enabled after the reference cell bit line is enabled and data is read, in a read operation of the phase change random access memory apparatus.

12. The phase change random access memory apparatus according to claim 8, wherein the reference voltage generating circuit is further configured to increase or decrease the reference voltage in accordance with the difference between the voltage level of the data stored in the reference cell and the voltage level of the reference voltage.

13. The phase change random access memory apparatus according to claim 12, wherein each of the at least one memory cell of the memory cell array and the reference cell are multi-level memory cells and the reference voltage is reference voltage for discriminating the most significant bit.

14. A read method of a phase change random access memory apparatus including at least one reference cell and a memory cell array, the read method comprising:

reading data of the reference cell in accordance with predetermined reference voltage;

generating a compensation reference voltage by controlling the reference voltage in accordance with the result of reading the data of the reference cell; and

reading data stored in at least one memory cell of the memory cell array on the basis of the compensation reference voltage.

15. The read method of a phase change random access memory apparatus according to claim 14, wherein the step of reading the data of the reference cell includes detecting the difference of voltage level between the voltage level of the reference voltage and the voltage level of the data stored in the reference cell.

16. The read method of a phase change random access memory apparatus according to claim 14, wherein the step of generating the compensation reference voltage includes increasing or decreasing the reference voltage in accordance with the difference of voltage level.

17. The read method of a phase change random access memory apparatus according to claim 14, wherein the data stored in the reference cell corresponds to data stored in the memory cell array.