ANALOG TO DIGITAL CONVERTER WITH LOW OUT OF BAND PEAKING

• US 20110075775A1
• Filed: 09/30/2009
• Published: 03/31/2011
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Piovaccari, Alessandro, Coban, Abdulkerim L.
• Granted Patent: US 7,928,878 B1
• Time in Patent Office: Days
• US Class Current: 375/350
• CPC Class Codes: H03M 3/344 by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
• CPC Class Codes: H03M 3/424 the quantiser being a multiple bit one
• CPC Class Codes: H03M 3/452 with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input
• CPC Class Codes: H03M 3/454 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Abstract

An analog to digital converter includes a delta sigma modulator with a modified distributed feed-forward (DFF) topology. The modulator includes low pass filter circuitry that provides a first path to a first integrator and a second, feed-forward path to a second integrator that significantly reduce the out of band signal transfer function (STF) peaking of the modulator.

Claims

1. A delta sigma modulator configured to receive an input signal, the delta sigma modulator comprising:

low pass filter circuitry configured to generate first and second signals responsive to the input signal;

an integrator configured to generate a third signal responsive to the first signal from the low pass filter circuitry; and

loop filter circuitry configured to generate a fourth signal responsive to the second signal from the low pass filter circuitry and the third signal from the integrator.

2. The delta sigma modulator of claim 1, further comprising:

analog to digital circuitry configured to generate an output signal responsive to the fourth signal from the loop filter circuitry and the third signal from the integrator.

3. The delta sigma modulator of claim 2, further comprising:

first digital to analog circuitry configured to generate a fifth signal responsive to the output signal from the analog to digital circuitry;

wherein the integrator is configured to generate the third signal responsive to the first signal from the low pass filter circuitry and the fifth signal from the first digital to analog circuitry.

4. The delta sigma modulator of claim 3, further comprising:

second digital to analog circuitry configured to generate a sixth signal;

wherein the analog to digital circuitry is configured to generate the output signal responsive to the fourth signal from the loop filter circuitry and the sixth signal from the second digital to analog circuitry.

5. The delta sigma modulator of claim 1 wherein the low pass filter circuitry includes a first low pass filter configured to generate the first signal responsive to the input signal and a second low pass filter configured to generate the second signal responsive to the input signal, and wherein a first corner frequency of the first low pass filter differs from a second corner frequency of the second low pass filter.

6. The delta sigma modulator of claim 1 wherein a first gain of the first signal differs from a second gain of the second signal.

7. The delta sigma modulator of claim 1 wherein the integrator and the loop filter comprise a plurality of continuous time integrators.

8. The delta sigma modulator of claim 1 wherein the integrator and the loop filter comprise a plurality of discrete time integrators.

9. The delta sigma modulator of claim 1 further comprising:

calibration circuitry configured to set an RC time constant of the low pass filter circuitry.

10. The delta sigma modulator of claim 1 further comprising:

calibration circuitry configured to set a first RC time constant of the integrator and a second RC time constant of the loop filter circuitry.

11. A communications device comprising:

a first low pass filter configured to output a first signal in response to an input signal;

a second low pass filter configured to output a second signal in response to the input signal;

an integrator configured to output a third signal in response to the first signal; and

loop filter circuitry configured to output a fourth signal in response to the second signal and the third signal.

12. The communications device of claim 11 wherein the integrator is configured to output the third signal in response to the first signal and the fourth signal.

13. The communications device of claim 12 further comprising:

analog to digital circuitry configured to convert the fourth signal to a digital signal; and

digital to analog circuitry configured to convert the digital signal to an analog signal and provide the analog signal to the integrator.

14. The communications device of claim 11 wherein a first corner frequency of the first low pass filter differs from a second corner frequency of the second low pass filter.

15. The communications device of claim 11 wherein a first gain of the first signal differs from a second gain of the second signal.

16. A media system comprising:

a communications device configured to receive an analog input signal and generate an output signal, the communications device includes;

low pass filter circuitry configured to generate first and second signals responsive to the analog input signal;

an integrator configured generate a third signal responsive to the first signal from the low pass filter circuitry;

loop filter circuitry configured to generate a fourth signal responsive to the third signal from the low pass filter circuitry and the third signal from the integrator;

analog to digital circuitry configured to generate a fifth signal responsive to the fourth signal from the loop filter circuitry and the third signal from the integrator; and

processing circuitry configured to generate the output signal responsive to the fifth signal from the analog to digital circuitry;

a processing unit configured to generate a media signal in response to the output signal from the communications device.

17. The media system of claim 16 further comprising:

a media output device configured to generate a media output in response to the media signal from the processing circuitry.

18. The media system of claim 17 further comprising:

an input/output unit configured to provide a control signal to the media output device.

19. The media system of claim 16 wherein the low pass filter circuitry includes a first low pass filter configured to generate the first signal responsive to the input signal and a second low pass filter configured to generate the second signal responsive to the input signal, and wherein a first corner frequency of the first low pass filter differs from a second corner frequency of the second low pass filter.

20. The media system of claim 16 wherein a first gain of the first signal differs from a second gain of the second signal.