SPLIT GATE NON-VOLATILE FLASH MEMORY CELL HAVING A FLOATING GATE, CONTROL GATE, SELECT GATE AND AN ERASE GATE WITH AN OVERHANG OVER THE FLOATING GATE, ARRAY AND METHOD OF MANUFACTURING

• US 20110076816A1
• Filed: 12/06/2010
• Published: 03/31/2011
• Est. Priority Date: 08/06/2007
• Status: Active Grant

• Current Assignee: Alexander Kotov, Amitay Levi, Chien-Sheng Su, James Yingbo Jia, Viktor Markov, Xian Liu, Yaw Wen Hu, Yuri Tkachev
• Original Assignee: Alexander Kotov, Amitay Levi, Chien-Sheng Su, James Yingbo Jia, Viktor Markov, Xian Liu, Yaw Wen Hu, Yuri Tkachev
• Inventors: Liu, Xian, Tkachev, Yuri, Markov, Viktor, Levi, Amitay, Jia, James Yingbo, Kotov, Alexander, Su, Chien-Sheng, Hu, Yaw Wen
• Granted Patent: US 7,927,994 B1
• Time in Patent Office: Days
• US Class Current: 438/264
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Claims

1-11. -11. (canceled)

12. A process of fabricating an array of non-volatile memory cells comprising:

forming a plurality of first region and second region spaced apart therefrom of a second conductivity type in a substrate of a first conductivity type;

forming staked pairs of control gates and floating gates above the substrate on opposite sides of the first region, with each stacked pair having a control gate position above a floating gate, positioned above the substrate, with each of the floating gate and control gate having a length measured in a direction from the first region to the second region, and with the control gate having a length less than the length of the floating gate with each floating gate closest to the first region having an exposed portion not covered above by the control gate, and having a tip, with a tunneling barrier covering said tip;

forming an erase gate above the first region on the substrate between a stacked pair of control gate and floating gate, with said erase gate having two portions;

a first portion between the exposed portions of the floating gates and insulated therefrom, and having a first end closest to the floating gate; and

a second portion electrically connected to the first portion, said second portion above the exposed portion of the floating gate and insulated therefrom by said tunneling barrier, shielding the tunneling barrier from the control gate, wherein said second portion of the erase gate separated from the floating gate by a first length measured in a direction substantially perpendicular to the length direction;

said second portion having a first end closest to the control gate, said second portion of the erase gate having a second length measured from the first end of the second portion of the erase gate to a vertical line aligned with the first end of the first portion of the erase gate in a direction substantially parallel to the length direction;

wherein said ratio of the second length to the first length is between approximately 1.0 and 2.5;

forming select gates above the substrate and between the stacked pair of control gate and floating gate and the second region.

13. The process of claim 12 wherein said select gates and said erase gates are formed in the same step.

14. The process of claim 13 wherein said selected gates and said erase gates are formed by depositing a layer of silicon over, between and beside the stacked gates, and removing portions of the silicon above the stacked gates and above the second regions.

15. The process of claim 12 wherein said first region is formed after the stacked pairs of control gates and floating gates are formed.

16. The process of claim 15 wherein said second region is formed after the select gates and erase gates are formed.

17. The process of claim 16 wherein said first regions and second regions are formed by ion implantation.

18-19. -19. (canceled)