INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
4 Assignments
0 Petitions
Accused Products
Abstract
In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
25 Citations
27 Claims
-
1-20. -20. (canceled)
-
21. A method for manufacturing an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a major surface of a semiconductor substrate, and a source-purpose conductive layer is provided on said major surface, comprising:
-
a step of forming a first semiconductor region within said semiconductor substrate; a step of forming a trench in said semiconductor substrate in such a manner that said trench penetrates said first semiconductor region; a step of forming a gate insulating film on a surface of said first semiconductor region which is exposed within said trench; a step in which a gate pillar made of both said gate-purpose conductive layer and a cap insulating film capping an upper surface of said gate-purpose conductive layer is formed in the trench where said gate insulating film is formed, and a portion of said gate pillar is projected from the major surface of said semiconductor substrate; a step of forming a second semiconductor region within said first semiconductor region which is segmented by said trench; a step of forming a side wall spacer on both said gate-purpose conductive layer and said cap insulating film of said projected portion of said gate pillar; and a step of forming said source-purpose conductive layer in a source contact region defined by said side wall spacer.
-
-
22. A method for manufacturing an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a major surface of a semiconductor substrate, and a source-purpose conductive layer is provided on said major surface, comprising:
-
a step of forming a first semiconductor region within said semiconductor substrate; a step of forming a plurality of trenches in said semiconductor substrate in such a manner that said trenches penetrate said first semiconductor region; a step of forming a gate insulating film on a surface of said first semiconductor region which is exposed within each of said trenches; a step in which each of said trenches where said gate insulating film is formed is embedded, and a portion of said gate-purpose conductive layer which is projected from the major surface of the semiconductor substrate is formed; a step of forming a second semiconductor region within said first semiconductor region which is segmented by said trenches; a step of forming a side wall spacer on a projected portion of said gate-purpose conductive layer and an insulating film covering an upper surface of said projected portion of said gate-purpose conductive layer; a step of forming a contact hole in a source contact region defined by said side wall spacer; and a step of forming said source-purpose conductive layer in said contact hole.
-
-
23. A method for manufacturing an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a major surface of a semiconductor substrate, and a source-purpose conductive layer is provided on said major surface, comprising:
-
a step of forming a first semiconductor region within said semiconductor substrate; a step of forming a trench in said semiconductor substrate in such a manner that said trench penetrates said first semiconductor region; a step of forming a gate insulating film on a surface of said first semiconductor region which is exposed within said trench; a step in which a gate pillar made of both said gate-purpose conductive layer and a cap insulating film capping an upper surface of said gate-purpose conductive layer is formed in the trench where said gate insulating film is formed, and a portion of said gate pillar is projected from the major surface of said semiconductor substrate; a step of forming a second semiconductor region within said first semiconductor region which is segmented by said trench; a step of forming a side wall spacer on both said gate-purpose conductive layer and said cap insulating film of said projected portion of said gate pillar; a step of forming a contact hole in said second semiconductor region, while said side wall spacer is employed as a mask; a step in which, after said contact hole has been formed, the side wall spacer is etched back so as to expose a surface of said second semiconductor region; and a step of forming said source-purpose conductive layer within exposed surface portions of said second semiconductor region and said contact hole.
-
-
24. A method of manufacturing a semiconductor device comprising the steps of:
-
(a) forming a gate trench in a main surface of a semiconductor substrate of a first conductivity type; (b) forming a gate insulating film over an inner wall and a bottom portion of the gate trench; (c) forming a gate electrode so as to fill the gate trench and a portion of which protrudes from the semiconductor substrate such that a width of the portion of the gate electrode is not less than a width of the gate electrode in the gate trench; (d) forming a sidewall over a side wall portion of the gate electrode protruding from the semiconductor substrate such that the height of an uppermost portion of the sidewall is higher than the height of an uppermost portion of the gate electrode; (e) forming a first semiconductor region, in the semiconductor substrate, of the first conductivity type serving as a source region; (f) forming, in the semiconductor substrate and below the first semiconductor region, a second semiconductor region of a second conductivity type opposite to the first conductivity type and serving as a channel region; (g) forming a body trench between sidewalls formed on adjacent gate electrodes by self-alignment with the gate electrodes, and so as to be deeper than a depth of the first semiconductor region; (h) forming a third semiconductor region at a bottom portion of the body trench and within the second semiconductor region, the third semiconductor region being of the second conductivity type and having an impurity concentration greater than an impurity concentration of the second semiconductor region; and (i) forming a fourth semiconductor region in an opposite surface to the main surface of the semiconductor substrate, the fourth semiconductor region being of the first conductivity type and serving as a drain region. - View Dependent Claims (25, 26, 27)
-
Specification