METHOD FOR MANUFACTURING CAPACITOR LOWER ELECTRODES OF SEMICONDUCTOR MEMORY

• US 20110076828A1
• Filed: 02/04/2010
• Published: 03/31/2011
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Inotera Memories Incorporated (Micron Technology, Inc.)
• Inventors: WANG, JUNG-HUNG, HUANG, SHIN BIN, CHANG, CHUNG-YI
• Granted Patent: US 8,088,668 B2
• Time in Patent Office: Days
• US Class Current: 438/396
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

A method for manufacturing capacitor lower electrodes of a semiconductor memory firstly forms a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs. Then a second stacked structure is formed on the first stacked structure; furthermore, a plurality of trenches extending from a top surface of the second stacked structure to a bottom surface of the first stacked structure are formed and expose the conducting plugs; finally, conductive metal materials and solid conducting cylindrical structures are deposited in the trenches in turn, and the conductive metal materials contact with the conductive plugs and the conducting cylindrical structures. Each conducting cylindrical structure is a capacitor lower electrode. Accordingly, the present invention can increase the supporting stress of the capacitor lower electrodes and further reduce the difficulty in disposing of capacitor upper electrodes and capacitor dielectric layers outside the capacitor lower electrodes.

Claims

1. A method for manufacturing capacitor lower electrodes of a semiconductor memory, comprising the steps of:

forming a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs;

etching the first stacked structure to form a plurality of first trenches in which the conductive plugs are exposed;

disposing a conductive metal material within each of the first trenches to cover the conductive plugs;

disposing a solid first conducting cylindrical structure within each of the first trenches, the first conducting cylindrical structures are deposited over the conductive metal materials;

forming a second stacked structure on the first stacked structure;

etching the second stacked structure to form a plurality of second trenches in which the first conducting cylindrical structures are exposed; and

disposing a solid second conducting cylindrical structure within each of the second trenches, second conducting cylindrical structures are deposited over the first conducting cylindrical structures.

2. The method as claimed in claim 1, wherein the first stacked structure includes two first insulating oxide layers, a first dielectric layer and a first insulating nitride layer, the first dielectric layer and the first insulating nitride layer are interposed there between the two first insulating oxide layers, the first insulating nitride layer is deposited onto the first dielectric layer, and the second stacked structure includes a second dielectric layer and a second insulating nitride layer from bottom to top.

3. The method as claimed in claim 2, further comprising the step of etching the first insulating oxide layers and the first insulating nitride layer to form a plurality of first grooves and then embedding a plurality of first dielectric boards in the first grooves before forming the first trenches.

4. The method as claimed in claim 2, further comprising the step of etching the second insulating nitride layer to form a plurality of second grooves before forming the second trenches.

5. The method as claimed in claim 4, further comprising the step of disposing a plurality of second dielectric boards into the second grooves after forming the second grooves.

6. The method as claimed in claim 2, further comprising the step of etching and removing the first dielectric layer and the second dielectric layer after forming the second conducting cylindrical structures.

7. The method as claimed in claim 2, wherein the first dielectric layer is an insulating material piece or a conductive material piece.

8. The method as claimed in claim 2, wherein the second dielectric layer is an insulating material piece or a conductive material piece.

9. The method as claimed in claim 3, where the first dielectric boards are insulating material pieces or conductive material pieces.

10. The method as claimed in claim 5, wherein the second dielectric boards are insulating material pieces or conductive material pieces.

11. A method for manufacturing capacitor lower electrodes of a semiconductor memory, comprising the steps of:

forming a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs;

forming a second stacked structure on the first stacked structure;

etching the first stacked structure and the second stacked structure to form a plurality of trenches extending from a top surface of the second stacked structure to a bottom surface of the first stacked structure, in which the conducting plugs are exposed in the trenches;

disposing a conductive metal material within each of the trenches to cover the conductive plugs; and

disposing a cylindrical capacitor lower electrode within each of the trenches, the capacitor lower electrodes are deposited over the conductive metal materials.

12. The method as claimed in claim 11, wherein the first stacked structure includes two first insulating oxide layers, a first dielectric layer and a first insulating nitride layer, the first dielectric layer and the first insulating nitride layer are interposed there between the two first insulating oxide layers, the first insulating nitride layer is disposed on the first dielectric layer, and the second stacked structure includes a second dielectric layer and a second insulating nitride layer from bottom to top.

13. The method as claimed in claim 12, further comprising the step of etching the first insulating oxide layers and the first insulating nitride layer to form a plurality of first grooves and then embedding a plurality of first dielectric boards into the first grooves before forming the second stacked structure.

14. The method as claimed in claim 12, further comprising the step of etching the second insulating nitride layer to form a plurality of second grooves before forming the trenches.

15. The method as claimed in claim 14, further comprising the step of disposing a plurality of second dielectric boards into the second grooves after forming the second grooves.

16. The method as claimed in claim 12, further comprising the step of etching and removing the first dielectric layer and the second dielectric layer after forming the capacitor lower electrodes.

17. The method as claimed in claim 12, wherein the first dielectric layer is an insulating material piece or a conductive material piece.

18. The method as claimed in claim 12, wherein the second dielectric layer is an insulating material piece or a conductive material piece.

19. The method as claimed in claim 13, wherein the first dielectric boards are insulating material pieces or conductive material pieces.

20. The method as claimed in claim 15, wherein the second dielectric boards are insulating material pieces or conductive material pieces.