ENHANCED MULTI-PROCESSOR WAVEFORM DATA EXCHANGE USING COMPRESSION AND DECOMPRESSION
First Claim
1. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, a method for compressing waveform data for storage in the second memory device, comprising:
- receiving a request at the memory controller from the processor to write the waveform data to the second memory device, wherein the waveform data comprise a plurality of samples represented in an integer data format or a floating-point data format;
receiving one or more compression control parameters from the processor at compression logic integrated with the memory controller;
receiving the plurality of samples at the compression logic in the memory controller from the first memory device in response to the request from the processor;
the compression logic compressing the plurality of samples in accordance with the compression control parameter to form a plurality of compressed samples for a compressed packet; and
transferring the compressed packet to the second memory device, the second memory device storing the compressed packet.
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Accused Products
Abstract
Configurable compression and decompression of waveform data in a multi-core processing environment improves the efficiency of data transfer between cores and conserves data storage resources. In waveform data processing systems, input, intermediate, and output waveform data are often exchanged between cores and between cores and off-chip memory. At each core, a single configurable compressor and a single configurable decompressor can be configured to compress and to decompress integer or floating-point waveform data. At the memory controller, a configurable compressor compresses integer or floating-point waveform data for transfer to off-chip memory in compressed packets and a configurable decompressor decompresses compressed packets received from the off-chip memory. Compression reduces the memory or storage required to retain waveform data in a semiconductor or magnetic memory. Compression reduces both the latency and the bandwidth required to exchange waveform data. This abstract does not limit the scope of the invention as described in the claims.
85 Citations
35 Claims
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1. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, a method for compressing waveform data for storage in the second memory device, comprising:
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receiving a request at the memory controller from the processor to write the waveform data to the second memory device, wherein the waveform data comprise a plurality of samples represented in an integer data format or a floating-point data format; receiving one or more compression control parameters from the processor at compression logic integrated with the memory controller; receiving the plurality of samples at the compression logic in the memory controller from the first memory device in response to the request from the processor; the compression logic compressing the plurality of samples in accordance with the compression control parameter to form a plurality of compressed samples for a compressed packet; and transferring the compressed packet to the second memory device, the second memory device storing the compressed packet. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, a method for decompressing waveform data retrieved from the second memory device, comprising:
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receiving at the memory controller a request from the processor to retrieve the waveform data from the second memory device, wherein the waveform data are represented by a plurality of compressed samples stored in the second memory device, wherein the plurality of compressed samples and one or more compression control parameters are contained in a compressed packet; receiving the compressed packet from the second memory device at decompression logic integrated with the memory controller in response to the request; the decompression logic decompressing the plurality of compressed samples of the compressed packet in accordance with the one or more compression control parameters to form a plurality of decompressed samples representing the waveform data; and providing the plurality of decompressed samples to the first memory device, the first memory device storing the plurality of decompressed samples for access by the processor. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, an apparatus for compressing waveform data for storage in the second memory device, comprising:
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the memory controller coupled to the processor and the first memory device, wherein the memory controller is operable to receive a request from the processor to write the waveform data to the second memory device, wherein the waveform data comprise a plurality of samples represented in an integer data format or a floating-point data format, the memory controller to retrieve the plurality of samples from the first memory device in response to the request; and compression logic integrated with the memory controller, the compression logic coupled to receive the plurality of samples retrieved from the first memory device and one or more compression control parameters from the processor, wherein the compression logic is operable to compress the plurality of samples in accordance with the one or more compression control parameters to form a plurality of compressed samples for a compressed packet, the compression logic coupled to provide the compressed packet to the second memory device for said storage. - View Dependent Claims (19, 20, 21, 22, 23, 24, 26, 27, 28)
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29. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, an apparatus for decompressing waveform data retrieved from the second memory device, comprising:
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the memory controller coupled to the processor and the first memory device, wherein the memory controller is operable to receive a request from the processor to read the waveform data from the second memory device, wherein the waveform data are represented by a plurality of compressed samples stored in the second memory device, wherein the plurality of compressed samples and one or more compression control parameters are contained in a compressed packet, the memory controller coupled to the second memory device to retrieve the compressed packet from the second memory device in response to the request; and decompression logic integrated with the memory controller, the decompression logic coupled to receive the compressed packet retrieved from the second memory device, wherein the decompression logic is operable to decompress the plurality of compressed samples in accordance with the one or more compression control parameters to form a plurality of decompressed samples representing the plurality of samples, the decompression logic coupled to provide the plurality of decompressed samples to the first memory device, the first memory device storing the plurality of decompressed samples for access by the processor. - View Dependent Claims (30, 31, 32, 33, 34, 35)
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Specification