METHOD FOR GENERATING MULTIPLE SERIAL BUS CHIP SELECTS USING SINGLE CHIP SELECT SIGNAL AND MODULATION OF CLOCK SIGNAL FREQUENCY

• US 20110078350A1
• Filed: 04/29/2010
• Published: 03/31/2011
• Est. Priority Date: 09/30/2009
• Status: Abandoned Application

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Carls, John M.
• Application Number:
  US12/770,398
• Publication Number:
  US 20110078350A1
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A system includes a serial bus having an electrical net for conveying a clock signal, and a master device and a plurality of slave devices coupled to the serial bus. The master device modulates a clock signal on its output on an electrical net according to first and second manners to select respective first and second of the slave devices. The first manner is distinct from the second manner. In alternate embodiments, the first and second manners are: (1) different frequencies of the clock signal; and (2) pulse trains on the clock signal with different predetermined numbers of clock edges prior to the assertion of a single slave select signal from the master device. In alternate embodiments: (1) each slave detects the first and second manners directly from the master; and (2) a distinct device detects the first and second manners from the master device and generates individual slave selects.

Claims

1. A device for individually selecting a plurality of slave devices coupled to a serial bus, the master device comprising:

a master serial port interface, configured for coupling to the serial bus, wherein the master serial port interface has an output for transmitting a clock signal from the master device to the plurality of slave devices; and

a processor, coupled to the master serial port interface, wherein the processor is configured to control the master serial port interface to;

modulate the clock signal on the output according to a first manner to select a first of the plurality of slave devices; and

modulate the clock signal on the output according to a second manner to select a second of the plurality of slave devices, wherein the first manner is distinct from the second manner.

2. The device of claim 1,

wherein the master serial port interface is configured to modulate the clock signal on the output according to the first manner by modulating the clock signal on the output at a first frequency during a first period;

wherein the master serial port interface is configured to modulate the clock signal on the output according to the second manner by modulating the clock signal on the output at a second frequency during a second period, wherein the first and second frequencies are distinct.

3. The device of claim 1, wherein the master serial port interface has a second output for transmitting a single slave select signal from the master device to the plurality of slave devices;

wherein the master serial port interface is configured to modulate the clock signal on the output according to the first manner by generating a pulse train with a first predetermined number of clock edges on the first output prior to asserting the slave select signal on the second output;

wherein the master serial port interface is configured to modulate the clock signal on the output according to the second manner by generating a pulse train with a second predetermined number of clock edges on the first output prior to asserting the slave select signal on the second output, wherein the first and second predetermined number of clock edges are distinct.

4. The device of claim 1, wherein the processor is further configured to control the master serial port interface to:

modulate the clock signal on the output according to a third manner to select a third of the plurality of slave devices, wherein the third manner is distinct from the first manner and the second manner.

5. The device of claim 1, wherein the device is comprised within a microprocessor.

18. The method of claim 1,

wherein said modulating the clock signal on the single electrical path according to the first manner comprises modulating the clock signal on the single electrical path at a first frequency during a first period;

wherein said modulating the clock signal on the single electrical path according to the second manner comprises modulating the clock signal on the single electrical path at a second frequency during a second period, wherein the first and second frequencies are distinct.

19. The method of claim 18, further comprising:

detecting the first frequency to determine that the master device is selecting the first of the plurality of slave devices; and

detecting the second frequency to determine that the master device is selecting the second of the plurality of slave devices.

20. The method of claim 19,

wherein said detecting the first frequency comprises determining that the first frequency is a first predetermined ratio of a reference clock signal frequency to determine that the master device is selecting the first of the plurality of slave devices;

and

wherein said detecting the second frequency comprises determining that the second frequency is a second predetermined ratio of the reference clock signal frequency to determine that the master device is selecting the second of the plurality of slave devices, wherein the first and second predetermined ratios are distinct.

21. The method of claim 19, wherein said detecting the first frequency is performed by the first of the plurality of slave devices, wherein said detecting the second frequency is performed by the second of the plurality of slave devices.

22. The method of claim 19, wherein said detecting the first frequency and said detecting the second frequency are performed by a device distinct from the master device and distinct from the plurality of slave devices.

23. The method of claim 22, further comprising:

asserting, by the distinct device, a first slave select signal to the first of the plurality of slave devices to select the first of the plurality of slave devices for the master device to communicate with, in response to said detecting the first frequency; and

asserting, by the distinct device, a second slave select signal to the second of the plurality of slave devices to select the second of the plurality of slave devices for the master device to communicate with, in response to said detecting the second frequency.

6. A system, comprising:

a serial bus, having an electrical net for conveying a clock signal;

a plurality of slave devices, coupled to the serial bus; and

a master device, coupled to the serial bus, wherein the master device comprises an output coupled to the electrical net for transmitting a clock signal to individually select the plurality of slave devices, wherein the master device is configured to;

modulate the clock signal on the output according to a first manner to select a first of the plurality of slave devices; and

modulate the clock signal on the output according to a second manner to select a second of the plurality of slave devices, wherein the first manner is distinct from the second manner.

7. The system of claim 6, further comprising:

a device distinct from the master device and distinct from the plurality of slave devices, wherein the distinct device is coupled to the master device and coupled to the plurality of slave devices, wherein the distinct device is configured to;

detect the first manner and responsively assert a first slave select signal to the first of the plurality of slave devices to select it for the master device; and

detect the second manner and responsively assert a second slave select signal to the second of the plurality of slave devices to select it for the master device.

8. The system of claim 7,

wherein to modulate the clock signal on the output according to the first manner, the master device is configured to modulate the clock signal on the output at a first frequency during a first period;

wherein to modulate the clock signal on the output according to the second manner, the master device is configured to modulate the clock signal on the output at a second frequency during a second period, wherein the first and second frequencies are distinct.

9. The system of claim 8,

wherein the distinct device is configured to determine that the first frequency is a first predetermined ratio of a reference clock signal frequency to determine that the master device is selecting the first of the plurality of slave devices;

wherein the distinct device is configured to determine that the second frequency is a second predetermined ratio of the reference clock signal frequency to determine that the master device is selecting the second of the plurality of slave devices, wherein the first and second predetermined ratios are distinct.

10. The system of claim 7, wherein the master device comprises a second output coupled to a second electrical net for transmitting a slave select signal to the distinct device;

wherein to modulate the clock signal on the first output according to the first manner, the master device is configured to generate a pulse train with a first predetermined number of clock edges on the first output prior to asserting the slave select signal on the second output;

wherein to modulate the clock signal on the first output according to the second manner, the master device is configured to generate a pulse train with a second predetermined number of clock edges on the first output prior to asserting the slave select signal on the second output, wherein the first and second predetermined number of clock edges are distinct.

11. The system of claim 10, wherein the distinct device comprises:

a counter, configured to;

reset its count and then commence counting clock edges on the first output, in response to detecting that the master device has deasserted the slave select signal on the second electrical net; and

stop counting in response to assertion of the slave select signal on the second electrical net;

wherein the distinct device is configured to assert the first slave select signal to the first of the plurality of slave devices to select it for the master device if the count is the first predetermined number;

wherein the distinct device is configured to assert the second slave select signal to the second of the plurality of slave devices to select it for the master device if the count is the second predetermined number.

12. The system of claim 6,

wherein the first of the plurality of slave devices is configured to detect the first manner of the modulation of the clock signal on the electrical net to detect that the master device is selecting the first of the plurality of slave devices;

wherein the second of the plurality of slave devices is configured to detect the second manner of the modulation of the clock signal on the electrical net to detect that the master device is selecting the second of the plurality of slave devices.

13. The system of claim 12,

wherein to detect the first manner of the modulation of the clock signal on the electrical net, the first of the plurality of slave devices is configured to detect the modulation of the clock signal on the electrical net at a first frequency during a first period;

wherein to detect the second manner of the modulation of the clock signal on the electrical net, the second of the plurality of slave devices is configured to detect the modulation of the clock signal on the electrical net at a second frequency during a second period, wherein the first and second frequencies are distinct.

14. The system of claim 13,

wherein to detect the modulation of the clock signal on the electrical net at a first frequency during a first period, the first of the plurality of slave devices is configured to determine that the first frequency is a first predetermined ratio of a reference clock signal frequency;

wherein to detect the modulation of the clock signal on the electrical net at a second frequency during a second period, the second of the plurality of slave devices is configured to determine that the second frequency is a second predetermined ratio of a reference clock signal frequency.

15. The system of claim 12, wherein the master device comprises a second output coupled to a second electrical net for transmitting a slave select signal to the plurality of slave devices;

wherein to detect the first manner of the modulation of the clock signal on the electrical net, the first of the plurality of slave devices is configured to detect a pulse train with a first predetermined number of clock edges on the first electrical net prior to assertion of the slave select signal on the second electrical net;

wherein to detect the second manner of the modulation of the clock signal on the electrical net, the second of the plurality of slave devices is configured to detect a pulse train with a second predetermined number of clock edges on the first electrical net prior to assertion of the slave select signal on the second electrical net, wherein the first and second predetermined number are distinct.

16. The system of claim 15, wherein each of the plurality of slave devices comprises:

a counter, configured to;

reset its count and then commence counting clock edges on the first output, in response to detecting that the master device has deasserted the slave select signal on the second electrical net; and

stop counting in response to assertion of the slave select signal on the second electrical net;

wherein the first of the plurality of slave devices is configured to detect that the master device is selecting it if the count is the first predetermined number;

wherein the second of the plurality of slave devices is configured to detect that the master device is selecting it if the count is the second predetermined number.

17. A method for a master device coupled to a serial bus to individually select a plurality of slave devices coupled to the serial bus, wherein the serial bus has a single electrical path for conveying a clock signal from the master device to the plurality of slave devices, the method comprising:

modulating the clock signal on the single electrical path according to a first manner to select a first of the plurality of slave devices; and

modulating the clock signal on the single electrical path according to a second manner to select a second of the plurality of slave devices, wherein the first manner is distinct from the second manner.

24. The method of claim 17, wherein the serial bus has a second single electrical path for conveying a slave select signal from the master device to the plurality of slave devices;

wherein said modulating the clock signal on the first single electrical path according to the first manner comprises generating a pulse train with a first predetermined number of clock edges on the first single electrical path prior to asserting the slave select signal on the second single electrical path; and

wherein said modulating the clock signal on the first single electrical path according to the second manner comprises generating a pulse train with a second predetermined number of clock edges on the first single electrical path prior to asserting the slave select signal on the second single electrical path, wherein the first and second predetermined number of clock edges are distinct.

25. The method of claim 24, further comprising:

detecting the pulse train with the first predetermined number of clock edges on the first single electrical path prior to asserting the slave select signal on the second single electrical path to determine that the master device is selecting the first of the plurality of slave devices; and

detecting the pulse train with the second predetermined number of clock edges on the first single electrical path prior to asserting the slave select signal on the second single electrical path to determine that the master device is selecting the second of the plurality of slave devices.

26. The method of claim 25, wherein said detecting the pulse train with the first predetermined number of clock edges on the first single electrical path prior to asserting the slave select signal on the second single electrical path is performed by the first of the plurality of slave devices, wherein said detecting the pulse train with the second predetermined number of clock edges on the first single electrical path prior to asserting the slave select signal on the second single electrical path is performed by the second of the plurality of slave devices.

27. The method of claim 25, wherein said detecting the pulse train with the first predetermined number of clock edges on the first single electrical path prior to asserting the slave select signal on the second single electrical path and said detecting the pulse train with the second predetermined number of clock edges on the first single electrical path prior to asserting the slave select signal on the second single electrical path are performed by a device distinct from the master device and distinct from the plurality of slave devices.

28. The method of claim 27, further comprising:

asserting, by the distinct device, a second slave select signal on a third single net to the first of the plurality of slave devices to select the first of the plurality of slave devices for the master device to communicate with, in response to said detecting the pulse train with the first predetermined number of clock edges on the first single electrical path prior to asserting the slave select signal on the second single electrical path; and

asserting, by the distinct device, a third slave select signal on a fourth single net to the second of the plurality of slave devices to select the second of the plurality of slave devices for the master device to communicate with, in response to said detecting the pulse train with the second predetermined number of clock edges on the first single electrical path prior to asserting the slave select signal on the second single electrical path.

29. The method of claim 25, further comprising:

commencing counting clock edges on the first single electrical path in response to deassertion of the slave select signal on the second single electrical path and stopping said counting in response to assertion of the slave select signal on the second single electrical path;

wherein said detecting the pulse train with the first predetermined number of clock edges on the first single electrical path comprises determining that the number of clock edges counted between said commencing and said stopping is the first predetermined number of clock edges;

wherein said detecting the pulse train with the second predetermined number of clock edges on the first single electrical path comprises determining that the number of clock edges counted between said commencing and said stopping is the second predetermined number of clock edges.

30. The method of claim 17, further comprising:

modulating the clock signal on the single electrical path according to a third manner to select a third of the plurality of slave devices, wherein the third manner is distinct from the first and second manners.