SOLID STATE STORAGE SYSTEM FOR CONTROLLING RESERVED AREA FLEXIBLY AND METHOD FOR CONTROLLING THE SAME

• US 20110078364A1
• Filed: 12/24/2009
• Published: 03/31/2011
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: LEE, Myung Suk, YANG, Wun Mo, KWAK, Jeong Soon
• Granted Patent: US 8,392,647 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A solid state storage system includes a flash memory area and a memory controller. The flash memory area includes memory blocks and replacement blocks configured to replace bad blocks occurring within the memory blocks. The memory controller is configured to perform a logical-to-physical address mapping on logical blocks including the replacement blocks, and select the replacement blocks using logical addresses of the logical blocks corresponding to the bad blocks.

Claims

1. A solid state storage system comprising:

a flash memory area comprising;

a plurality of memory blocks; and

a plurality of replacement blocks configured to replace bad blocks occurring within the memory blocks; and

a memory controller configured to perform a logical-to-physical address mapping on logical blocks comprising the replacement blocks, and select a replacement block among the plurality of replacement blocks using logical addresses of the logical blocks corresponding to the bad blocks.

2. The solid state storage system according to claim 1, wherein the memory controller sets a pointer configured to determine positions and selection order of the replacement blocks.

3. The solid state storage system according to claim 2, wherein, when a bad block occurs, the memory controller selects a replacement block corresponding to the bad block, the replacement block having a logical address corresponding to a resulting value obtained by decreasing a maximum logical address of the logical block according to a value of the pointer.

4. The solid state storage system according to claim 3, wherein a range of the replacement block is defined by an initial value and an upper limit value of the pointer.

5. A solid state storage system, comprising:

a flash memory area comprising;

a plurality of memory blocks; and

a plurality of replacement blocks configured to replace bad blocks occurring within the memory blocks; and

a memory controller configured to allocate logical addresses and physical addresses to the replacement blocks, select a replacement block corresponding to a bad block when the bad block occurs, and perform a wear leveling on extra replacement blocks not used to replace the bad blocks.

6. The solid state storage system according to claim 5, wherein the memory controller sets a pointer configured to determine positions and selection order of the replacement blocks.

7. The solid state storage system according to claim 6, wherein, when a bad block occurs, the memory controller selects a replacement block corresponding to the bad block, the replacement block having a logical address corresponding to a resulting value obtained by decreasing a maximum logical address of the logical block according to a value of the pointer.

8. The solid state storage system according to claim 6, wherein the memory controller increments the value of the pointer when a bad block occurs.

9. The solid state storage system according to claim 5, wherein the memory controller maintains a logical address of the bad block, and replaces a physical address of the bad block with a physical address of the replacement block.

10. The solid state storage system according to claim 6, wherein the memory controller performs the wear leveling on the replacement blocks as normal data blocks by using a final stored pointer.

11. The solid state storage system according to claim 6, wherein a maximum value of the pointer is a total number of blocks included in the replacement blocks.

12. The solid state storage system according to claim 11, wherein a range of the replacement block is defined by an initial value and an upper limit value of the pointer.

13. A method for controlling a solid state storage system, comprising:

creating an address mapping table regarding all logical blocks, including replacement blocks;

when bad blocks occur calculating logical addresses of the replacement blocks by using a maximum logical address of the logical blocks and a pointer;

replacing physical addresses of the bad blocks with physical addresses mapped into the calculated replacement blocks; and

performing a wear leveling on extra replacement blocks not used to replace the bad blocks.

14. The method according to claim 13, wherein creating the address mapping table comprises initializing the pointer configured to determine positions and selection order of reserved areas.

15. The method according to claim 13, wherein calculating the logical addresses of the logical blocks included in reserved areas comprises decreasing the maximum logical address of the logical blocks according to a value of the pointer.

16. The method according to claim 13, wherein replacing the physical addresses of the bad block comprises maintaining logical addresses of the bad blocks, and replacing physical addresses of the bad blocks with physical addresses of the logical blocks of a selected reserved area.

17. The method according to claim 13, further comprising determining whether the logical block having the logical address calculated using a final stored pointer is replaced or not during the wear leveling.

18. The method according to claim 17, wherein when the logical block having the calculated logical address is not a replacement target block, the replacement block is determined as an extra replacement block, and the wear leveling is performed on the replacement block as a normal data block.