MEMORY DEVICE AND DATA ACCESS METHOD

• US 20110078393A1
• Filed: 04/08/2010
• Published: 03/31/2011
• Est. Priority Date: 09/29/2009
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: Lin, Jen-Wen
• Granted Patent: US 8,417,901 B2
• Time in Patent Office: Days
• US Class Current: 711/155
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The invention provides a data access method. First, a plurality of commands received from a host is stored in a command queue. A plurality of logical address ranges of the commands is then calculated. A plurality of write commands is then selected from the commands, wherein the logical address ranges of the write commands are overlapping with each other. Whether at least one read command having a receiving order that is in between the receiving orders of the write commands exists in the command queue is then determined. When the at least one read command does not exist, write data corresponding to the write commands are combined together to obtain combined write data according to the logical address ranges of the write commands. A combined write command and the combined write data are then sent to a memory to request that the memory executes the write commands.

Claims

1. A data access method for a memory, comprising:

storing a plurality of commands received from a host in a command queue;

calculating a plurality of logical address ranges of the commands;

selecting a plurality of write commands from the commands stored in the command queue, wherein the logical address ranges of the write commands are overlapping with each other;

determining whether at least one read command having a receiving order that is in between the receiving orders of the write commands exits in the command queue;

when the at least one read command does not exist, combining write data corresponding to the write commands together to obtain combined write data according to the logical address ranges of the write commands; and

sending a combined write command and the combined write data to the memory to request that the memory executes the write commands.

2. The data access method as claimed in claim 1, wherein the data access method further comprises:

when the at least one read command exists, determining whether the logical address range of the at least one read command is overlapping with an overlapping segment of the logical address ranges of the write commands;

when the logical address range of the at least one read command does not overlap with the overlapping segment, combining the write data corresponding to the write commands together to obtain the combined write data according to the logical address ranges of the write commands; and

sending the combined write command and the combined write data to the memory to request that the memory executes the write commands.

3. The data access method as claimed in claim 1, wherein calculation of the logical address ranges of the commands comprise:

obtaining a plurality of starting logical addresses of the commands;

obtaining a plurality of data lengths of the commands; and

estimating the logical address ranges of the commands according to the starting logical addresses and the data lengths.

4. The data access method as claimed in claim 1, wherein combination of the write data comprises:

determining a plurality of overlapping segments of the logical address ranges of the write commands;

removing data corresponding to the overlapping segments from the write data of the write commands together to obtain amended write data corresponding to non-overlapping logical address ranges; and

combining the amended write data together to obtain the combined write data.

5. The data access method as claimed in claim 1, wherein the commands comprise a first write command and a second write command, and the logical address range of the first write command is determined to be overlapping with the logical address range of the second write command when the starting logical address corresponding to the first write command is in between the starting logical address and the ending logical address corresponding to the second write command, or when the starting logical address corresponding to the second write command is in between the starting logical address and the ending logical address corresponding to the first write command.

6. The data access method as claimed in claim 1, wherein the data access method further comprises:

after the combined write command and the combined write data are sent to the memory, deleting the write commands from the command queue.

8. The memory device as claimed in claim 6, wherein when the at least one read command exists, the controller determines whether the logical address range of the at least one read command is overlapping with an overlapping segment of the logical address ranges of the write commands, and when the logical address range of the at least one read command does not overlap with the overlapping segment, the controller combines the write data corresponding to the write commands together to obtain the combined write data according to the logical address ranges of the write commands, and sends the combined write command and the combined write data to the memory to request that the memory executes the write commands.

7. A memory device, coupled to a host, comprising:

a memory, for data storage; and

a controller, storing a plurality of commands received from the host in a command queue, calculating a plurality of logical address ranges of the commands, selecting a plurality of write commands with logical address ranges overlapping with each other from the commands stored in the command queue, determining whether at least one read command having a receiving order that is in between the receiving orders of the write commands exits in the command queue, combining write data corresponding to the write commands together to obtain combined write data according to the logical address ranges of the write commands when the at least one read command does not exist, and sending a combined write command and the combined write data to the memory to request that the memory executes the write commands.

9. The memory device as claimed in claim 7, wherein when the controller calculates the logical address ranges of the commands, the controller obtains a plurality of starting logical addresses of the commands, obtains a plurality of data lengths of data of the commands, and estimates the logical address ranges of the commands according to the starting logical addresses and the data lengths.

10. The memory device as claimed in claim 7, wherein when the controller combines the write data together, the controller determines a plurality of overlapping segments of the logical address ranges of the write commands, removes data corresponding to the overlapping segments from the write data of the write commands together to obtain amended write data corresponding to non-overlapping logical address ranges, and combines the amended write data together to obtain the combined write data.

11. The memory device as claimed in claim 7, wherein the commands comprise a first write command and a second write command, and the controller determines that the logical address range of the first write command is overlapping with the logical address range of the second write command when the starting logical address corresponding to the first write command is in between the starting logical address and the ending logical address corresponding to the second write command, or when the starting logical address corresponding to the second write command is in between the starting logical address and the ending logical address corresponding to the first write command.

12. The memory device as claimed in claim 7, wherein after the combined write command and the combined write data are sent to the memory, the controller deletes the write commands from the command queue.

13. A data access method for a memory, comprising:

storing a plurality of commands received from a host in a command queue;

calculating a plurality of logical address ranges of the commands;

selecting a plurality of write commands from the commands stored in the command queue, wherein the logical address ranges of the write commands correspond to a specific page of the memory;

determining whether at least one read command having a receiving order that is in between the receiving orders of the write commands exists in the command queue;

when the at least one read command does not exist, combining write data corresponding to the write commands together to obtain combined write data according to the logical address ranges of the write commands; and

sending a combined write command and the combined write data to the memory to request that the memory executes the write commands.

14. The data access method as claimed in claim 13, wherein the data access method further comprises:

when the at least one read command exists, determining whether the logical address range of the at least one read command corresponds to the specific page of the memory;

when the logical address range of the at least one read command does not correspond to the specific page, combining the write data corresponding to the write commands together to obtain the combined write data according to the logical address ranges of the write commands; and

sending the combined write command and the combined write data to the memory to request that the memory executes the write commands.

15. The data access method as claimed in claim 13, wherein calculation of the logical address ranges of the commands comprise:

obtaining a plurality of starting logical addresses of the commands;

obtaining a plurality of data lengths of the commands; and

estimating the logical address ranges of the commands according to the starting logical addresses and the data lengths.

16. The data access method as claimed in claim 13, wherein combination of the write data comprises:

storing the write data corresponding to the write commands in a buffer according to the logical address ranges of the write commands; and

outputting data stored in the buffer to obtain the combined write data;

wherein the data capacity of the buffer is equal to the data capacity of the specific page.

17. The data access method as claimed in claim 13, wherein the commands comprise a first write command, and the logical address range of the first write command is determined to be corresponding to the specific page of the memory when the starting logical address corresponding to the first write command is subsequent to a starting logical address of the specific page and the ending logical address corresponding to the first write command is prior to an ending logical address of the specific page.

18. The data access method as claimed in claim 13, wherein the data access method further comprises:

after the combined write command and the combined write data are sent to the memory, deleting the write commands from the command queue.

19. A memory device, coupled to a host, comprising:

a memory, for data storage; and

a controller, storing a plurality of commands received from the host in a command queue, calculating a plurality of logical address ranges of the commands, selecting a plurality of write commands with logical address ranges corresponding to a specific page of the memory from the commands stored in the command queue, determining whether at least one read command having a receiving order that is in between the receiving orders of the write commands exists in the command queue, combining write data corresponding to the write commands together to obtain combined write data according to the logical address ranges of the write commands when the at least one read command does not exist, and sending a combined write command and the combined write data to the memory to request that the memory executes the write commands.

20. The memory device as claimed in claim 19, wherein when the at least one read command exists, the controller determines whether the logical address range of the at least one read command corresponds to the specific page of the memory, and when the logical address range of the at least one read command does not correspond to the specific page, the controller combines the write data corresponding to the write commands together to obtain the combined write data according to the logical address ranges of the write commands, and sends the combined write command and the combined write data to the memory to request that the memory executes the write commands.

21. The memory device as claimed in claim 19, wherein when the controller calculates the logical address ranges of the commands, the controller obtains a plurality of starting logical addresses of the commands, obtains a plurality of data lengths of the commands, and estimates the logical address ranges of the commands according to the starting logical addresses and the data lengths.

22. The memory device as claimed in claim 19, wherein when the controller combines the write data together, the controller stores the write data corresponding to the write commands in a buffer according to the logical address ranges of the write commands, and outputs data stored in the buffer to obtain the combined write data, wherein the data capacity of the buffer is equal to the data capacity of the specific page.

23. The memory device as claimed in claim 19, wherein the commands comprise a first write command, and the controller determines that the logical address range of the first write command corresponds to the specific page of the memory when the starting logical address corresponding to the first write command is subsequent to a starting logical address of the specific page and the ending logical address corresponding to the first write command is prior to an ending logical address of the specific page.

24. The memory device as claimed in claim 19, wherein after the combined write command and the combined write data are sent to the memory, the controller deletes the write commands from the command queue.