TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT

• US 20110078427A1
• Filed: 09/29/2009
• Published: 03/31/2011
• Est. Priority Date: 09/29/2009
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Salinas, Daniel, Wang, Nicholas, Heinrich, Steven J., Choquette, Jack, Nickolls, John R., Thorn, Tommy, Kalaiah, Aravind, Shebanow, Michael C., Siu, Ming Y., Coon, Brett W.
• Granted Patent: US 8,522,000 B2
• Time in Patent Office: Days
• US Class Current: 712/244
• CPC Class Codes: G06F 9/327 for interrupts
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.

Claims

1. A method for handling a disruption event occurring during execution of a first thread group within a multiprocessor of a parallel processing subsystem residing within a computer system, the method comprising:

receiving notification of the disruption event;

halting execution of all thread groups executing within the multiprocessor;

setting an error status register to indicate a type of the disruption event; and

setting, for each thread group, a program counter to point to a memory address of a trap handler code segment that comprises a software routine that configures the multiprocessor to handle the disruption event.

2. The method of claim 1, wherein the step of halting execution of all thread groups comprises waiting for all instructions pipelined for execution by all thread groups executing within the multiprocessor to complete.

3. The method of claim 1, wherein the step of halting execution of all thread groups comprises maintaining sufficient state of the multiprocessor during execution in order to roll back all instructions pipelined for execution.

4. The method of claim 1, wherein the disruption event is selected from the group consisting of exceptions generated by a first thread of the thread group and interrupts generated externally from the execution of the first thread group.

5. The method of claim 1, wherein the threads associated with each thread group executing within the multiprocessor concurrently execute, and the thread groups are allocated time slices in the multiprocessor.

6. The method of claim 1, further comprising the steps of:

determining that the first thread group is executing in the trap handler code segment;

providing a value in the error status register in response to an instruction in the trap handler code segment for reading the error status register; and

executing instructions in a sub-segment of the trap handler code segment to handle the disruption event.

7. The method of claim 6, further comprising the steps of:

waiting for each of the other thread groups executing in the multiprocessor to either complete execution within the trap handler code or yield execution flow to a host CPU residing within the computer system; and

returning to a code segment of the first thread group prior to encountering the disruption event.

8. The method of claim 6, wherein the step of executing instructions in the sub-segment of the trap handler code segment includes executing an instruction to transmit an interrupt to a host CPU residing within the computer system to notify the host CPU of the disruption event.

9. The method of claim 1, further comprising the steps of:

identifying a second thread group that is waiting for at least one other thread group at a synchronization barrier instruction; and

unwinding execution of the synchronization barrier instruction by the second thread group to facilitate entrance into the trap handler code segment for the second thread group.

10. A graphics processing unit (GPU) configured to handle a disruption event occurring during execution of a first thread group within a multiprocessor of the GPU, the GPU comprising:

a trap handler controller configured to perform the steps of receiving notification of the disruption event, halting execution of all thread groups executing within the multiprocessor, setting an error status register to indicate a type of the disruption event, and setting, for each thread group, a program counter to point to a memory address of a trap handler code segment that comprises a software routine that configures the multiprocessor to handle the disruption event; and

a memory unit comprising the trap handler code segment including instructions, that when executed by the multiprocessor, performs the steps of requesting a value of the error status register, branching to a sub-segment in the trap handler code segment that comprises instructions for addressing the type of disruption event, and executing instructions in the sub-segment of the trap handler code segment to handle the disruption event.

11. The GPU of claim 10, wherein the trap handler controller is further configured to perform the steps of determining that the first thread group is executing in the trap handler code segment, providing a value in the error status register in response to an instruction in the trap handler code segment for reading the error status register, and executing instructions in a sub-segment of the trap handler code segment to handle the disruption event.

12. The GPU of claim 10, wherein the step of executing instructions in the sub-segment of the trap handler code segment includes executing an instruction to transmit an interrupt to a host CPU residing within the computer system to notify the host CPU of the disruption event.

13. The GPU of claim 10, wherein the trap handler controller is further configured to perform the steps of waiting for each of the other thread groups executing in the multiprocessor to either complete execution within the trap handler code or yield execution flow to a host CPU residing within the computer system, and returning to a code segment of the first thread group prior to encountering the disruption event.

14. The GPU of claim 10, wherein the trap handler controller is further configured to perform the steps of identifying a second thread group that is waiting for at least one other thread group at a synchronization barrier instruction, and unwinding execution of the synchronization barrier instruction by the second thread group to facilitate entrance into the trap handler code segment for the second thread group.

15. The GPU of claim 10, wherein the disruption event is selected from the group consisting of exceptions generated by a first thread of the thread group and interrupts generated externally from the execution of the first thread group.

16. The GPU of claim 10, wherein the threads associated with each thread group executing within the multiprocessor concurrently execute, and the thread groups are allocated time slices in the multiprocessor.

17. The GPU of claim 10, further comprising a register file comprising the error status register, the program counter, a register for storing the memory address of the trap handler code segment, and a register for storing an identification of the first thread group.

18. A computer-readable medium including trap handler instructions that, when executed by a multiprocessor of a parallel processing subsystem of a computer system, cause the multiprocessor to handle a disruption event occurring during execution of a first thread group within the multiprocessor by performing the steps of:

requesting a value of an error status register set by a trap handler controller to indicate a type of the disruption event;

branching to a sub-segment in the trap handler instructions that comprises instructions for addressing the type of disruption event; and

executing instructions in the sub-segment in the trap handler instructions to handle the disruption event.

19. The computer-readable medium of claim 18, wherein prior to executing the trap handler instructions, the multiprocessor has received notification of the disruption event, halted execution of all thread groups executing within the multiprocessor, set the error status register to indicate the type of the disruption event;

and set, for each thread group, a program counter to point to a memory address of a start of the trap handler instructions.

20. The computer-readable medium of claim 18, wherein upon completion of executing the instructions in the sub-segment in the trap handler instructions, the microprocessor further performs the steps of:

waiting for each of the other thread groups executing in the multiprocessor to either complete execution within the trap handler instructions or yield execution flow to a host CPU residing within the computer system; and

returning to a code segment of the current thread group prior to encountering the disruption event.

21. The computer readable medium of claim 18, wherein the step of executing instructions in the sub-segment of the trap handler instructions includes executing an instruction to transmit an interrupt to a host CPU residing within the computer system to notify the host CPU of the disruption event.

22. The computer readable medium of claim 18, wherein prior to executing the trap handler instructions, the microprocessor further performs the steps of:

identifying a second thread group that is waiting for at least one other thread group at a synchronization barrier instruction; and

unwinding execution of the synchronization barrier instruction by the second thread group to facilitate entrance into the trap handler instructions for the second thread group.

23. The computer readable medium of claim 18, wherein the disruption event is selected from the group consisting of exceptions generated by a first thread of the thread group and interrupts generated externally from the execution of the first thread group.