Method and Circuit Configuration for Simulating Fault States in a Control Unit

• US 20110078526A1
• Filed: 01/16/2007
• Published: 03/31/2011
• Est. Priority Date: 02/22/2006
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Koehrer, Mathias, Geiselmann, Robert, Jakoby, Henrik, Mohr, Paul
• Granted Patent: US 8,589,139 B2
• Time in Patent Office: Days
• US Class Current: 714/741
• CPC Class Codes: G01R 31/007 using microprocessors or computers
• CPC Class Codes: G01R 31/2844 using test interfaces, e.g. adapters, test boxes, switches, PIN drivers G01R31/2889 takes precedence
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G01R 31/50 Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections testing of sparking plugs H01T13/58
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A method and a circuit configuration for simulating fault states in a control unit, as well as a computer program and a computer-program product, are provided. In this context, a multiplexer and a fault-generating circuit are used, the multiplexer being realized using a relay technology, and the fault-generating circuit being implemented using a semiconductor technology.

Claims

1-14. -14. (canceled)

15. A method for simulating a fault state in a control unit, comprising:

connecting terminals of the control unit to a fault-generating circuit via a multiplexer, wherein the multiplexer is realized using a relay technology, and wherein the fault-generating circuit is implemented using a semiconductor technology; and

simulating a fault state using the fault-generating circuit.

16. The method as recited in claim 15, wherein the simulating of the fault state includes:

a) pre-configuring a fault in one step; and

b) activating the pre-configured fault in another step.

17. The method as recited in claim 16, wherein the simulating of the fault includes simulating a line interruption.

18. The method as recited in claim 16, wherein the simulating of the fault includes simulating a short-circuit at a selected potential of a voltage.

19. The method as recited in claim 16, wherein the simulating of the fault includes simulating a contact corrosion at a control-unit terminal.

20. The method as recited in claim 16, wherein the simulating of the fault includes simulating a short-circuit of two control-unit terminals.

21. The method as recited in claim 16, wherein the simulating of the fault includes simulating a crosstalk between two control-unit terminals.

22. The method as recited in claim 16, wherein the simulating of the fault includes simulating line losses due to leakage currents at a control-unit terminal.

23. A circuit arrangement configured to simulate a fault state in a control unit, comprising:

a multiplexer realized using a relay technology; and

a fault-generating circuit connected to the multiplexer via a signal line, wherein the fault-generating circuit is implemented using a semiconductor technology, and wherein the fault-generating circuit generates a fault.

24. The circuit configuration as recited in claim 23,

wherein the fault-generating circuit includes a transistor logic.

25. The circuit configuration as recited in claim 24, wherein the transistor logic is implemented using a MOSFET technology.

26. The circuit configuration as recited in claim 24, further comprising:

a microcontroller configured to control a simulation of the fault.

27. A computer-readable storage medium storing a computer program having program codes which, when executed on a computer, control a method for simulating a fault state in a control unit, the method comprising:

connecting terminals of the control unit to a fault-generating circuit via a multiplexer, wherein the multiplexer is realized using a relay technology, and wherein the fault-generating circuit is implemented using a semiconductor technology; and

simulating a fault state, wherein the simulating of the fault state includes;

a) pre-configuring a fault in one step; and

b) activating the pre-configured fault in another step.