Firing Cell

• US 20110080454A1
• Filed: 02/06/2008
• Published: 04/07/2011
• Est. Priority Date: 02/06/2008
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Heineck, Matthew P., Maxfield, David, Ghozeil, Adam L., Mackenzie, Mark H., Mar, Eugene J., Phillips, Andrew
• Granted Patent: US 8,511,796 B2
• Time in Patent Office: Days
• US Class Current: 347/62
• CPC Class Codes: B41J 2/04541 Specific driving circuit
• CPC Class Codes: B41J 2/04543 Block driving
• CPC Class Codes: B41J 2/0455 Details of switching sections of circuit, e.g. transistors
• CPC Class Codes: B41J 2/0458 controlling heads based on heating elements forming bubbles

Abstract

A system is provided that includes first means for pre-charging a node to a first potential where the node coupled to a switch configured to control current through a firing resistor and second means for selectively discharging the node to a second potential across a path that has only one transistor between the node and the second potential.

Claims

1. A system comprising:

a firing resistor;

a switch coupled to a node and configured to control current through the firing resistor;

first means for pre-charging the node to a first potential;

a first transistor; and

second means for selectively discharging the node to a second potential across at least a first at that has only the first transistor between the node and the second potentials.

2. The system of claim 1 further comprising:

a second transistor; and

third means for selectively discharging the node to the second potential across a second path that has only the second transistor between the node and the second potential.

3. The system of claim 1 further comprising:

third means for attenuating a signal used by the first means to pre-charge the node.

4. The system of claim 1 further comprising:

third means for biasing the second means during a first pre-charge cycle to ensure that the node sufficiently discharges prior to a second pre-charge cycle that is subsequent to the first pre-charge cycle.

5. The system of claim 4 further comprising:

fourth means for attenuating a signal used to bias the second means.

6. The system of claim 1 wherein the second means is responsive to at least one address signal.

7. The system of claim 1 wherein the second means is responsive to a data signal.

8. The system of claim 1 wherein the switch includes a transistor with a gate terminal connected to the node.

9. A method comprising:

providing a tiring resistor configured to cause ink to be ejected from a nozzle when energized and a switch to control the energy applied to the firing resistor;

providing first circuitry configured to pre-charge a terminal of the switch to a first potential; and

providing second circuitry that selectively connects the terminal of the switch to a second potential across at least a first path that includes only a first transistor subsequent to the switch being pre-charged to the first potential.

10. The method of claim 9 where the first potential turns on the switch and the second potential turns off the switch.

11. The method of claim 9 wherein the first circuitry pre-charges the terminal of the switch to the first potential using at least one signal that is attenuated by third circuitry.

12. The method of claim 9 wherein the second circuitry selectively connects the terminal of the switch to the second potential in response to a select signal and at least one address signal.

13. The method of claim 9 wherein the second circuitry selectively connects the terminal of the switch to the second potential in response to a select signal and a data signal.

14. A firing cell comprising:

a firing resistor;

a switch connected to a node and configured control current through the firing resistor;

pre-charge circuitry configured to pre-charge the node; and

a first transistor having a first terminal connected to the node and a second terminal connected to a reference potential and configured to selectively discharge the node to the reference potential.

15. The firing cell of claim 14 further comprising:

a second transistor having a first terminal connected to the node and a second terminal connected to the reference potential and configured to selectively discharge the node to the reference potential.

16. The firing cell of claim 15 wherein the first transistor configured to selectively discharge the node to the reference potential in response to at least on address signal, and wherein the second transistor configured to selectively discharge the node to the reference potential in response to a data signal.

17. The firing cell of claim 14 further comprising:

a distributed level shifter configured to generate a pre-charge signal from an input signal and an attenuated signal generated from the input signal;

wherein the pre-charge circuitry is configured to pre-charge the node using the pre-charge signal.

18. The firing cell of claim 17 further comprising:

buffer circuitry configured to be biased by the pre-charge signal end configured to control the operation of the first transistor.

19. The firing cell of claim 14 wherein the firing resistor, the switch, the pre-charge circuitry, and the first transistor are formed using a CMOS process.

20. The firing cell of claim 14 wherein the switch includes a second transistor with a gate connection directly coupled to the node.