LOW-POWER POLICY FOR PORT

• US 20110080919A1
• Filed: 11/03/2009
• Published: 04/07/2011
• Est. Priority Date: 10/07/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ding, Jin, Kwan, Bruce
• Granted Patent: US 8,456,992 B2
• Time in Patent Office: Days
• US Class Current: 370/419
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Various example embodiments are disclosed. According to an example embodiment, a method may include determining, by a port processor, a buffer length based on an amount of data stored in a port controlled by the port processor, comparing the buffer length to a low-power buffer threshold, determining a link utilization based on a number of packets transmitted by the port, comparing the link utilization to a link utilization threshold, and placing the port into a low-power state based on the comparison of the buffer length to the low-power buffer threshold and the comparison of the link utilization to the link utilization threshold.

Claims

1. A method comprising:

determining, by a port processor, a buffer length based on an amount of data stored for a port controlled by the port processor;

comparing the buffer length to a low-power buffer threshold;

determining a link utilization based on a number of packets transmitted by the port;

comparing the link utilization to a link utilization threshold; and

placing the port into a low-power state based on the comparison of the buffer length to the low-power buffer threshold and the comparison of the link utilization to the link utilization threshold.

2. The method of claim 1, wherein the determining the link utilization includes determining the link utilization based on the number of packets transmitted by the port over a link utilization time interval.

3. The method of claim 1, wherein placing the port into the low power state includes placing the port into the low power state based on the buffer length being less than the low-power buffer threshold and the link utilization being less than the link utilization threshold.

4. The method of claim 1, further including the port ceasing transmission of packets based on the port processor placing the port into the low-power state.

5. The method of claim 1, further comprising:

removing the port from the low-power state based on;

an aging timer expiring; and

comparing the buffer length to a timer expiration buffer threshold upon expiration of the aging timer.

6. The method of claim 1, further comprising:

comparing the buffer length to an active buffer threshold; and

removing the port from the low-power state based on comparison of the buffer length to the active buffer threshold.

7. The method of claim 1, further comprising:

comparing the buffer length to an active buffer threshold; and

removing the port from the low-power state based on the buffer length exceeding the active buffer threshold.

8. The method of claim 1, further comprising receiving the packets from a memory management unit.

9. An apparatus comprising:

a port processor, the port processor being configured to;

determine a buffer length based on an amount of data stored for a port controlled by the port processor;

compare the buffer length to a low-power buffer threshold;

determine a link utilization based on a number of packets transmitted by the port;

compare the link utilization to a link utilization threshold; and

place the port in a low-power state based on the comparison of the buffer length to the low-power buffer threshold and the comparison of the link utilization to the link utilization threshold.

10. The apparatus of claim 9, wherein the port processor is further configured to:

remove the port from the low-power state based on the buffer length exceeding an active buffer threshold.

11. The apparatus of claim 9 wherein the port processor is configured to determine the link utilization based on the number of packets transmitted by the port over a link utilization time interval.

12. The apparatus of claim 9,

wherein the port configured to transmit packets, and

wherein the port is configured to cease transmission of packets upon entering the low-power state.

13. The apparatus of claim 9, wherein the port processor is further configured to:

determine when an aging interval has expired;

upon the expiration of the aging interval, compare the buffer length to a timer expiration buffer threshold; and

remove the port from the low-power state based on the comparison of the buffer length to the timer expiration buffer threshold.

14. The apparatus of claim 9, wherein, when the port is in the low-power state, the port processor is configured to respond to the port receiving a packet by:

comparing the buffer length to an active buffer threshold; and

removing the port from the low-power state based on the comparison of the buffer length to the active buffer threshold.

15. The apparatus of claim 9, wherein the port is configured to transmit the packets according to an IEEE 802.3 Ethernet protocol.

16. The apparatus of claim 9, wherein the port processor further includes:

a buffer length register configured to store the buffer length;

a low-power buffer threshold register configured to store the low-power buffer threshold;

a link utilization register configured to store the link utilization; and

a link utilization threshold register configured to store the link threshold;

wherein the port processor is configured to;

update the buffer length register in response to receiving a buffer length signal from the port;

update the link utilization register based on the port transmitting the packets;

compare the buffer length stored in the buffer length register to the low-power buffer threshold stored in the low-power buffer threshold register;

compare the link utilization stored in the link utilization register to the link utilization threshold stored in the link threshold register; and

place the port in the low-power state based on;

the comparison of the buffer length to the low-power buffer threshold; and

the comparison of the link utilization to the link utilization threshold.

17. The apparatus of claim 16, wherein the port processor further includes:

an aging interval register configured to store a value corresponding to a number of clock cycles in an aging interval; and

an aging timer register,

wherein the port processor is configured to;

decrement the aging timer register at each clock cycle;

remove the port from the low-power state when the aging timer register reaches an aging timer floor if the buffer length exceeds a timer expiration buffer threshold; and

restore the aging timer register to the value stored in the aging interval register when the aging timer register reaches the timer floor.

18. The apparatus of claim 9, wherein the port processor further includes:

an aging timer configured to determine when an aging interval has expired,

wherein the port processor is configured to respond to the aging interval'"'"'s expiration by;

determining whether the buffer length is non-zero; and

removing the port from the low-power state if the buffer length is non-zero.

19. The apparatus of claim 9, further comprising:

a memory management unit, the memory management unit including;

a shared memory configured to store packets destined for the port or a second port; and

a dedicated memory configured to store packets destined for the port,

the memory management unit being configured to determine whether to forward packets to the first port or the second port,

wherein the second port is configured to transmit packets out of the apparatus.

20. An apparatus comprising:

a memory management unit configured to;

store packets received by the apparatus; and

route the packets to either a first port or a second port;

the first port being coupled to or including a first port processor, and the first port being configured to;

receive and store packets from the memory management unit;

send a buffer length signal to the first port processor, the buffer length signal indicating a number of packets stored for the first port; and

transmit the received packets out of the apparatus when the first port is in an active state, but not transmit the received packets out of the apparatus when the first port is in a low-power state,

wherein the first port processor includes;

a buffer length register configured to store the buffer length based on the buffer length signal;

a low-power buffer threshold register configured to store a low-power buffer threshold;

a link utilization register configured to store a link utilization based on a number of packets transmitted by the first port processor;

a link utilization threshold register configured to store a link utilization threshold;

an aging interval register configured to store a value corresponding to a number of clock cycles in an aging interval; and

an aging timer register,

wherein the port processor is configured to;

update the buffer length register in response to receiving the buffer length signal from the first port;

update the link utilization register in response to the port transmitting packets;

compare the buffer length stored in the buffer length register to the low-power buffer threshold stored in the low-power buffer threshold register;

compare the link utilization stored in the link utilization register to the link utilization threshold stored in the link utilization threshold register; and

place the port in the low-power state based on;

the comparison of the buffer length to the low-power buffer threshold; and

the comparison of the link utilization to the link utilization threshold; and

the second port configured to receive packets from the memory management unit and transmit the received packets out of the apparatus.