Method for Forming a Shielded Gate Trench FET

• US 20110081773A1
• Filed: 12/02/2010
• Published: 04/07/2011
• Est. Priority Date: 06/26/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Scott L. Hunt
• Inventors: Hunt, Scott L.
• Granted Patent: US 8,129,241 B2
• Time in Patent Office: Days
• US Class Current: 438/589
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for forming a shielded gate field effect transistor (FET) includes forming a plurality of trenches in a semiconductor region and forming a shield electrode in a bottom portion of each trench. The method also includes forming a dielectric layer comprising a first oxide layer and a nitride layer both laterally extending over the shield electrode. The method also includes forming a gate electrode over the dielectric layer.

Claims

1-24. -24. (canceled)

25. A method for forming a shielded gate field effect transistor (FET), the method comprising:

forming a plurality of trenches in a semiconductor region;

forming a shield electrode in a bottom portion of each trench;

forming a dielectric layer comprising a first oxide layer and a nitride layer both laterally extending over the shield electrode; and

forming a gate electrode over the dielectric layer.

26. The method of claim 25 wherein forming the dielectric layer comprises:

(i) forming the first oxide layer;

(ii) forming the nitride layer over the first oxide layer; and

(iii) forming a second oxide layer over the nitride layer.

27. The method of claim 25 further comprising:

forming a shield dielectric layer lining lower sidewalls and a bottom of each trench, wherein top surfaces of the shield dielectric are recessed relative to a top surface of the shield electrode so as to form recesses adjacent to opposing sides of the shield electrode, the first oxide layer and the nitride layer filling the recesses.

28. The method of claim 27 wherein the first oxide layer and the nitride layer overlap the shield electrode along a depth of the plurality of trenches.

29. The method of claim 25 wherein the nitride layer further extends vertically along upper sidewalls of each trench between the gate electrode and the semiconductor region.

30. The method of claim 29 wherein the first oxide layer is formed using a thermal oxidation process which also results in formation of an oxide layer vertically extending along upper sidewalls of each trench.

31. The method of claim 30 wherein a thickness of the laterally extending first oxide layer is greater than a thickness of the oxide layer vertically extending along the upper sidewalls of each trench.

32. A method for forming a shielded gate field effect transistor (FET), the method comprising:

forming a plurality of trenches in a semiconductor region;

forming a shield dielectric lining opposing sidewalls and bottom of each trench;

forming a shield electrode in a bottom portion of each trench over the shield dielectric;

recessing the shield dielectric below a top surface of the shield electrode so as to form recesses between an upper portion of the shield electrode and the semiconductor region;

forming a nitride layer over the shield electrode in each trench, the nitride layer partially filling the recesses; and

forming a gate electrode in an upper portion of each trench over the nitride layer.

33. The method of claim 32 further comprising:

forming a dielectric layer extending between the shield electrode and the gate electrode, the dielectric layer comprising;

(i) a first oxide layer,

(ii) the nitride layer over the first oxide layer, and

(iii) a second oxide layer over the nitride layer, wherein at least the first oxide layer and the nitride layer fill the recesses and overlap the shield electrode along a depth of the plurality of trenches.

34. The method of claim 32 wherein the nitride layer further extends vertically along upper sidewalls of each trench between the gate electrode and the semiconductor region.

35. The method of claim 32 wherein the first oxide layer is formed using a thermal oxidation process which also results in formation of an oxide layer vertically extending along upper sidewalls of each trench.

36. The method of claim 35 wherein a thickness of the laterally extending first oxide layer is greater than a thickness of the oxide layer vertically extending along the upper sidewalls of each trench.