PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE

• US 20110082965A1
• Filed: 10/01/2009
• Published: 04/07/2011
• Est. Priority Date: 10/01/2009
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: McCracken, Michael Oliver, Schwetman, Herbert Dewitt JR., Bonebakker, Jan Lodewijk, Koka, Pranay
• Granted Patent: US 8,176,220 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/214 Solid state disk

Abstract

A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.

Claims

1. A system comprising a plurality of nodes coupled using a network of processor buses, wherein the plurality of nodes comprises:

a first processor node comprising one or more processing cores and main memory; and

a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses, the flash memory node comprising;

a flash memory comprising a plurality of flash pages;

a first memory comprising;

a cache partition for storing cached flash pages for the plurality of flash pages in the flash memory; and

a control partition for storing cache control data and contexts of requests to access the plurality of flash pages; and

a logic module comprising a direct memory access (DMA) register and configured to;

receive a first request from the first processor node via the first processor bus to access the plurality of flash pages, wherein the first request is received using the DMA register that is mapped into an address space of the first processor node,

store one or more parameters of the first request as a first context of the contexts stored in the control partition of the first memory,

schedule a DMA operation responsive to the first request, and

perform the DMA operation based on the first context,

wherein the DMA operation transfers data between the flash memory and the first processor node and comprises accessing the cache partition in the first memory when a portion of the plurality of flash pages is cached in the cache partition according to the cache control data.

2. The system of claim 1,

wherein performing the DMA operation further comprises issuing a command of the processor bus to transfer data between the flash memory and the first processor node,

wherein the logic module is further configured to generate an interrupt to the processor when the DMA operation is completed, and

wherein the flash memory node further comprises a second memory for storing cached portions of the control partition of the first memory.

3. The system of claim 1,

wherein the control partition of the first memory further comprises a flash page address mapping table,

wherein the logic module is further configured to generate, based on the flash page address mapping table, a cached flash page address in the cache partition from a flash page address comprised in the one or more parameters, and

wherein the DMA operation is performed based at least on the cached flash page address.

4. The system of claim 1,

wherein the flash memory is a virtual memory paging device for the first processor node,

wherein the control partition of the first memory further comprises a virtual address mapping table,

wherein the logic module is further configured to generate, based on the virtual address mapping table, at least one of a flash page address in the flash memory and a cached flash page address in the cache partition from a virtual address comprised in the one or more parameters, and

wherein the DMA operation is based on the at least one of the flash page address in the flash memory and the cached flash page address in the cache partition.

5. The system of claim 2,

wherein the first request is generated by a first thread executing on a first processor core of the one or more processor cores in the first processor node,

wherein the logic module is further configured to:

receive a second request via a second processor bus to access the plurality of flash pages, wherein the second request is generated by a second thread running on one of a group consisting of the first processor core and a second processor core, wherein the second processor core is located in one of a group consisting of the first processor node and a second processor node of the plurality of processor nodes, the second processor node coupled to the flash memory node via the second processor bus of the processor buses;

store the second request as a second context of the contexts stored in the control partition of the first memory;

schedule a second DMA operation responsive to the second request; and

perform the second DMA request based on the second context concurrently with the first DMA operation.

6. A method for accessing a processor-bus-connected flash storage module (PFSM) operatively coupled to a processor via a processor bus, the PFSM comprising a flash memory, a buffer memory, and a processor accessible command register mapped into an address space of the processor, the method comprising:

receiving a page access request from the processor via the processor bus using the processor accessible command register;

storing one or more parameters of the page access request in the buffer memory as a context of the page access request;

scheduling a flash memory access responsive to receiving a trigger parameter of the one or more parameters;

performing the scheduled flash memory access based on the context; and

issuing a command of the processor bus in conjunction with performing the scheduled flash memory access to transfer data between the PFSM and the processor.

7. The method of claim 6, further comprising:

scheduling a direct memory access (DMA) operation responsive to receiving the trigger parameter,

wherein the DMA operation comprises performing the flash memory access and the command of the processor bus.

8. The method of claim 6, further comprising:

generating an interrupt to the processor when the command of the processor bus and the flash memory access are completed.

9. The method of claim 6, wherein the flash memory and a cache partition of the buffer memory forms a memory hierarchy of the PFSM, the method further comprising:

performing a cache operation according to a cache policy of the memory hierarchy responsive to receiving the trigger parameter, wherein the flash memory access is scheduled responsive to performing the cache operation.

10. The method of claim 9, wherein the PFSM further comprises a flash page address mapping table, the method further comprising:

generating, based on the flash page address mapping table, a cached flash page address in the cache partition from a flash page address comprised in the one or more parameters,

wherein the cache operation is based on the cached flash page address.

11. The method of claim 9, wherein the PFSM further comprises a virtual address mapping table for implementing a virtual memory paging device, the method further comprising:

generating, based on the virtual address mapping table, at least one of a flash page address in the flash memory and a cached flash page address in the cache partition from a virtual address comprised in the one or more parameters,

wherein the cache operation and the flash memory access are based on the at least one of the flash page address in the flash memory and the cached flash page address in the cache partition.

12. A method for accessing a virtual memory of a processor using a processor-bus-connected flash storage module (PFSM) as a first paging device and a hard disk drive (HDD) as a second paging device, the PFSM operatively coupled to the processor via a processor bus, the PFSM comprising a flash memory and a virtual address mapping table, the method comprising:

allocating a first address partition and a second address partition of the virtual memory for a software application of the processor to the first paging device and the second paging device, respectively;

identifying a virtual memory page in the first paging device responsive to a page fault of the virtual memory triggered by the software application;

sending a page access request to the PFSM for accessing the virtual memory page responsive to the page fault, wherein the page access request is sent via the processor bus and comprises a virtual address of the virtual memory page; and

receiving the virtual memory page from the PFSM based on a command of the processor bus issued by the PFSM in conjunction with performing a flash memory access in the flash memory using a flash page address, wherein the virtual address mapping table translates the virtual address of the virtual memory page to the flash page address in the flash memory.

13. The method of claim 12, wherein defining the first address partition and the second address partition of the virtual memory is based on a memory access pattern of the software application.

14. The method of claim 12, further comprising:

defining the first address partition and the second address partition of the virtual memory when an operating system of the processor is starting up.

15. The method of claim 12, further comprising:

defining the first address partition and the second address partition of the virtual memory when the software application of the processor is starting up.

16. The method of claim 12, further comprising:

defining the first address partition and the second address partition of the virtual memory when the software application of the processor requests memory from an operating system of the processor.

17. The method of claim 12, wherein the PFSM further comprises a buffer memory and a processor accessible command register mapped into an address space of the processor, the method further comprising:

storing, by the PFSM, one or more parameters of the page access request in the buffer memory as a context of the page access request, wherein the one or more parameters are received by the PFSM using the processor accessible command register; and

scheduling, by the PFSM, a direct memory access (DMA) operation responsive to receiving a trigger parameter of the one or more parameters,

wherein the DMA operation comprises performing the flash memory access and the command of the processor bus.

18. The method of claim 17, further comprising:

generating, by the PSFM, an interrupt to the processor when the DMA operation is completed.

19. The method of claim 17, wherein the flash memory and a cache partition of the buffer memory forms a memory hierarchy of the PFSM, the method further comprising:

performing a cache operation by the PFSM according to a cache policy of the memory hierarchy responsive to receiving the trigger parameter, wherein the flash memory access is scheduled as a result of the cache operation.

20. The method of claim 17, further comprising:

identifying a cached flash page address in the cache partition for the virtual address based on the virtual address mapping table,

wherein the cache operation is based on the cached flash page address in the cache partition.