DATA PROCESSING ARCHITECTURES FOR PACKET HANDLING

• US 20110083000A1
• Filed: 12/10/2010
• Published: 04/07/2011
• Est. Priority Date: 02/14/2001
• Status: Active Grant

• Current Assignee: Anthony Spencer, Danny Halamish, Gajinder Panesar, Gordon Faulds, Jeff Bond, John Rhoades, Ken Cameron, Matthias Dejaegher, Paul Winser, Ray Mcconnell, Simon Mcintosh-Smith
• Original Assignee: Anthony Spencer, Danny Halamish, Gajinder Panesar, Gordon Faulds, Jeff Bond, John Rhoades, Ken Cameron, Matthias Dejaegher, Paul Winser, Ray Mcconnell, Simon Mcintosh-Smith
• Inventors: Bond, Jeff, McIntosh-Smith, Simon, McConnell, Ray, Halamish, Danny, Rhoades, John, Spencer, Anthony, Dejaegher, Matthias, Panesar, Gajinder, Cameron, Ken, Winser, Paul, Faulds, Gordon
• Granted Patent: US 8,127,112 B2
• Time in Patent Office: Days
• US Class Current: 712/22
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: H04L 12/56 Packet switching systems
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof

Abstract

A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.

Claims

1. A data processing architecture, comprising:

an input device for receiving an incoming stream of data packets of unpredictable size; and

a plurality of processing elements which are operable to process the received data packets;

wherein the input device is operable to distribute a data packet of unpredictable size across one or more processing elements, the number of which is dynamically determined based at least in part on the size of the data packet;

wherein the data processing architecture is operable to process at least one data packet at a time; and

wherein the processing elements are arranged in a single instruction multiple data (SIMD) array and are operable to process different respective packet protocols at once while executing a single common instruction stream.

2. A data processing architecture as claimed in claim 1, wherein the number of processing elements across which a data packet is distributed depends on the number of processing elements that are required to store said packet.

3. A data processing architecture as claimed in claim 1, wherein the input device is operable to transfer data packets to one or more of the processing elements, but is not required to transfer data packets to all of the processing elements.

4. A data processing architecture as claimed in claim 1, comprising an SIMD data processing architecture, wherein at least one of the plurality of processing elements is operable to enter a standby mode of operation in dependence upon data received by that processing element.

5. A data processing architecture as claimed in claim 1, wherein at least one of the plurality of processing elements is operable to enter a standby mode of operation when no data is distributed to the processing element.

6. A data processing architecture as claimed in claim 1, wherein the plurality of processing elements comprise a first plurality of parallel arrays of processing elements, and a second plurality of hardware accelerator units.

7. A data processing architecture as claimed in claim 1, comprising a plurality of parallel arrays of said processing elements, and a data input/output system that is operable to transfer data to and from the arrays of processing elements in turn.

8. A data processing architecture as claimed in claim 1, wherein each processing element is operable to process data stored by that element in accordance with processing steps determined by the data so stored.

9. A data processing architecture as claimed in claim 1, comprising one or more of:

a single instruction multiple data (SIMD) processing element array;

a data input device, a data output device;

a hardware accelerator;

a data packet buffer; and

a bus structure for connecting the functional blocks to one another.

10. A data processing architecture as claimed in claim 1, implemented in any of a single integrated circuit, a plurality of integrated circuits, and a processor.

11. A data processing architecture as claimed in claim 6, further comprising:

an output device operable to collect processor data packets from the processing elements and to construct an outgoing data packet stream from collected processor data packets.

12. A data processing architecture as claimed in claim 4, wherein said input device and an output device comprise part of an input/output system that is operable to transmit data to, and receive data from, the processing elements.

13. A data processing architecture as claimed in claim 1, wherein processing is only performed by processing elements containing packets or packet portions carrying a header.

14. A data processing architecture as claimed in claim 1, wherein processing is performed by multiple processing elements containing portions of a packet, in dependence on either data in the packet or information about the packet.

15. A data processing architecture as claimed in claim 1, wherein the number of processing elements is determined based on a bandwidth and an amount of required processing.

16. A data processing architecture as claimed in claim 1, wherein the size of the packet portions is determined based on a bandwidth and an amount of required processing.

17. A data processing architecture as claimed in claim 1, wherein the input device is operable to distribute batches of data packets of unpredictable size across said processing elements, wherein:

a data packet greater than a predetermined size is divided into portions and each portion distributed to a respective processing element; and

a data packet less than a predetermined size is distributed to a single processing element.

18. A data processing architecture as claimed in claim 17, wherein the portions are of a fixed size.

19. A data processing architecture as claimed in claim 17, wherein the processing elements are operable to control the transfer of packet portions to the processing elements from the input device.

20. A data processing architecture as claimed in claim 17, wherein the processing elements are operable to control the transfer of packet portions from the processing elements to an output device.